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F28069 SCIB receive interrupt doesn't occur

decai wang
Expert 1590 points

Other Parts Discussed in Thread: SYSBIOS

Hi,sir!

It is very strange! I initialize SCIA and SCIB all same setting(fifo mode, bute 1byte trigger level,),  but SCIA  receiving interrupt is OK.

But SCIB rx interrupt doesn't occur, I had tested Example_2806xSci_Echoback , and SCIB is also ok in polling mode.

So do I miss something ?

in fact, SCIA and SCIB rx intterupt are all done by SYSBIOS HWI ISR. SCIA RX ISR is OK. but SCIB RX ISR is something wrong.

SCIA RX INTNUM is 96 ,and SCIB RX INTNUM is 98.

I also search related in E2E forum. it seems someone also had this issue.

http://e2e.ti.com/support/microcontrollers/c2000/f/171/p/35175/122981.aspx#122981 

// TI File $Revision: /main/2 $
// Checkin $Date: January 4, 2011 10:10:40 $
//###########################################################################
//
// FILE: F2806x_Sci.c
//
// TITLE: F2806x SCI Initialization & Support Functions.
//
//###########################################################################
// $TI Release: 2806x C/C++ Header Files and Peripheral Examples V1.00 $
// $Release Date: January 11, 2011 $
//###########################################################################

#include "F2806x_Device.h" // F2806x Headerfile Include File
#include "F2806x_Examples.h" // F2806x Examples Include File

//#define SCIHB 0x0000 //when 90MHz 22500000/(baudrate*8)-1
//#define SCILB 0x00A2
//#define SCILB 0x0081

typedef struct
{
int SCIHB;
int SCILB;
}BaudReg_t;
const BaudReg_t BAUDRATE[] =
{
{0x0009,0x0027}, //1200
{0x0002,0x0049}, //4800
{0x0001,0x0024}, //9600
{0x0000,0x0091}, //19200
{0x0000,0x0048}, //38400
};
//---------------------------------------------------------------------------
// InitSci:
//---------------------------------------------------------------------------
// This function initializes the SCI(s) to a known state.
//
void InitSci(void)
{
// Initialize SCI-A:
SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
SciaRegs.SCICTL2.bit.TXINTENA =1;
SciaRegs.SCICTL2.bit.RXBKINTENA =1;
SciaRegs.SCIHBAUD = BAUDRATE[3].SCIHB;
SciaRegs.SCILBAUD = BAUDRATE[3].SCILB;
SciaRegs.SCICCR.bit.LOOPBKENA =0; // disable loop back

SciaRegs.SCIFFTX.all=0xE040; //no FIFO INT, clear TXFIFINT
// SciaRegs.SCIFFRX.all=0x2021; //enable RX,FIFO
SciaRegs.SCIFFRX.all=0x2021; //enable RX,FIFO
SciaRegs.SCIFFCT.all=0x00;

SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
SciaRegs.SCIFFRX.bit.RXFIFORESET=1;

// Initialize SCI/B:


ScibRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
ScibRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
ScibRegs.SCICTL2.bit.TXINTENA =1;
ScibRegs.SCICTL2.bit.RXBKINTENA =1;
ScibRegs.SCIHBAUD = BAUDRATE[3].SCIHB; //9600
ScibRegs.SCILBAUD = BAUDRATE[3].SCILB; //9600
ScibRegs.SCICCR.bit.LOOPBKENA =0; // disable loop back
ScibRegs.SCIFFTX.all=0xE040;//enable RX,FIFO
//no FIFO INT, clear TXFIFINT
ScibRegs.SCIFFRX.all=0x2021;
ScibRegs.SCIFFCT.all=0x00;

ScibRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
ScibRegs.SCIFFTX.bit.TXFIFOXRESET=1;
ScibRegs.SCIFFRX.bit.RXFIFORESET=1;

//tbd...

}

//---------------------------------------------------------------------------
// Example: InitSciGpio:
//---------------------------------------------------------------------------
// This function initializes GPIO pins to function as SCI pins
//
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO
// inputs after reset.
//
// Caution:
// Only one GPIO pin should be enabled for SCITXDA/B operation.
// Only one GPIO pin shoudl be enabled for SCIRXDA/B operation.
// Comment out other unwanted lines.

void InitSciGpio()
{
#if DSP28_SCIA
InitSciaGpio();
#endif // endif DSP28_SCIA
#if DSP28_SCIB
InitScibGpio();
#endif // endif DSP28_SCIB
}

#if DSP28_SCIA
void InitSciaGpio()
{
EALLOW;

/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled disabled by the user.
// This will enable the pullups for the specified pins.

GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up for GPIO28 (SCIRXDA)
// GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up for GPIO7 (SCIRXDA)

GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up for GPIO29 (SCITXDA)
// GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up for GPIO12 (SCITXDA)

/* Set qualification for selected pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.

GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (SCIRXDA)
// GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3; // Asynch input GPIO7 (SCIRXDA)

/* Configure SCI-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be SCI functional pins.

GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPIO28 for SCIRXDA operation
// GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2; // Configure GPIO7 for SCIRXDA operation

GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPIO29 for SCITXDA operation
// GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; // Configure GPIO12 for SCITXDA operation

EDIS;
}
#endif // endif DSP28_SCIA

#if DSP28_SCIB
void InitScibGpio()
{
EALLOW;

/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled disabled by the user.
// This will enable the pullups for the specified pins.

GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up for GPIO11 (SCIRXDB)
// GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up for GPIO15 (SCIRXDB)
// GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (SCIRXDB)
// GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up for GPIO23 (SCIRXDB)
// GpioCtrlRegs.GPBPUD.bit.GPIO41 = 0; // Enable pull-up for GPIO41 (SCIRXDB)
// GpioCtrlRegs.GPBPUD.bit.GPIO44 = 0; // Enable pull-up for GPIO44 (SCIRXDB)

GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up for GPIO9 (SCITXDB)
// GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up for GPIO14 (SCITXDB)
// GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (SCITXDB)
// GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up for GPIO22 (SCITXDB)
// GpioCtrlRegs.GPBPUD.bit.GPIO40 = 0; // Enable pull-up for GPIO40 (SCITXDB)
// GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up for GPIO58 (SCITXDB)

/* Set qualification for selected pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.

GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Asynch input GPIO11 (SCIRXDB)
// GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (SCIRXDB)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SCIRXDB)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (SCIRXDB)
// GpioCtrlRegs.GPBQSEL1.bit.GPIO41 = 3; // Asynch input GPIO41 (SCIRXDB)
// GpioCtrlRegs.GPBQSEL1.bit.GPIO44 = 3; // Asynch input GPIO44 (SCIRXDB)


/* Configure SCI-B pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be SCI functional pins.

GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 2; // Configure GPIO11 for SCIRXDB operation
// GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; // Configure GPIO15 for SCIRXDB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; // Configure GPIO19 for SCIRXDB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; // Configure GPIO23 for SCIRXDB operation
// GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 2; // Configure GPIO41 for SCIRXDB operation
// GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 2; // Configure GPIO44 for SCIRXDB operation


GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 2; // Configure GPIO9 for SCITXDB operation
// GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; // Configure GPIO14 for SCITXDB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; // Configure GPIO18 for SCITXDB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; // Configure GPIO22 for SCITXDB operation
// GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 2; // Configure GPIO40 for SCITXDB operation
// GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 2; // Configure GPIO58 for SCITXDB operation


EDIS;
}
#endif // endif DSP28_SCIB

//===========================================================================
// End of file.
//===========================================================================

  • 0
    Guru 192875 points

    Hi,

    Check with the attached project:

    5342.scia_loopback_interrupts.rar

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    Expert 1590 points

    Hi.

    This is a  demo code from TI resource explore. and I had tested it.  but It cannot solve my problem. after I rewrite similar code for SCIB, SCIB rx interrupt cannot occur.it seems SCIB behavior is not the same as SCIA.

    So ,Can you share me a demo code whic can run at  SCIB intterrupt(no fifo mode.just single byte rx interrupt,tx interrupt is disable)?

    Thanks! 

  • 0 in reply to decai wang
    Expert 1590 points

    In polling mode, SCIB  receiving  or sending is OK. so the connection, basic SCIB settings are OK. but it cannot work at interrupt mode.

  • 0 in reply to decai wang
    Guru 192875 points

    Hi,

    Did you go through the SCIB initialization routine. This might be in a different file, please check if the interupts are enabled for the same. Also check with the interrupt related files in your project. I'll also try to check the same from my end and will let you know.

    Regards,

    Gautam

  • 0 in reply to decai wang
    Guru 13185 points

    Hello,

    Please check whether your have enable your SCIB clock (in InitSysCtrl())

    SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1;     // SCI-B

    Hope this solves your problem.

    Best regards,

    Maria

  • 0 in reply to Maria Todorova
    Expert 1590 points

    Of course, it is. and I test SCIB in  polling mode,it is OK. but t cannot work at interrupt mode.

  • 0 in reply to decai wang
    Guru 192875 points

    Hi DW,

    Here's a working code for you :)

    Fullscreen 1263.scib_interrupt.c Download 
    #include "DSP28x_Project.h"     // Device Headerfile and Examples Include File

#define CPU_FREQ    90E6
#define LSPCLK_FREQ CPU_FREQ/4
#define SCI_FREQ    100E3
#define SCI_PRD     (LSPCLK_FREQ/(SCI_FREQ*8))-1

// Prototype statements for functions found within this file.
__interrupt void ScibTxFifoIsr(void);
__interrupt void ScibRxFifoIsr(void);
__interrupt void ScibTxFifoIsr(void);
__interrupt void ScibRxFifoIsr(void);
void Scib_fifo_init(void);
void Scib_fifo_init(void);
void error(void);

// Global variables
Uint16 sdataA[2];    // Send data for SCI-A
Uint16 rdataA[2];    // Received data for SCI-A
Uint16 rdata_pointA; // Used for checking the received data

void main(void)
{
   Uint16 i;

// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2806x_SysCtrl.c file.
   InitSysCtrl();

// Step 2. Initalize GPIO:
// This example function is found in the F2806x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio();
// Setup only the GP I/O only for SCI-A and SCI-B functionality
// This function is found in F2806x_Sci.c
   InitSciGpio();

// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
   DINT;

// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2806x_PieCtrl.c file.
   InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
   IER = 0x0000;
   IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2806x_DefaultIsr.c.
// This function is found in F2806x_PieVect.c.
   InitPieVectTable();

// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
   EALLOW;  // This is needed to write to EALLOW protected registers
   PieVectTable.SCIRXINTB = &ScibRxFifoIsr;
   PieVectTable.SCITXINTB = &ScibTxFifoIsr;
   EDIS;   // This is needed to disable write to EALLOW protected registers

// Step 4. Initialize all the Device Peripherals:
// This function is found in F2806x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
   Scib_fifo_init();  // Init SCI-A

// Step 5. User specific code, enable interrupts:

// Init send data.  After each transmission this data
// will be updated for the next transmission
   for(i = 0; i<2; i++)
   {
      sdataA[i] = i;
   }

   rdata_pointA = sdataA[0];
// Enable interrupts required for this example
   PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   // Enable the PIE block
   PieCtrlRegs.PIEIER9.bit.INTx1=1;     // PIE Group 9, INT1
   PieCtrlRegs.PIEIER9.bit.INTx2=1;     // PIE Group 9, INT2
   IER = 0x100; // Enable CPU INT
   EINT;

// Step 6. IDLE loop. Just sit and loop forever (optional):
    for(;;);

}

void error(void)
{
   __asm("     ESTOP0"); // Test failed!! Stop!
    for (;;);
}

__interrupt void ScibTxFifoIsr(void)
{
    Uint16 i;
    for(i=0; i< 2; i++)
    {
       ScibRegs.SCITXBUF=sdataA[i];     // Send data
    }

    for(i=0; i< 2; i++)                 //Increment send data for next cycle
    {
       sdataA[i] = (sdataA[i]+1) & 0x00FF;
    }

    ScibRegs.SCIFFTX.bit.TXFFINTCLR=1;  // Clear SCI Interrupt flag
    PieCtrlRegs.PIEACK.all|=0x100;      // Issue PIE ACK
}

__interrupt void ScibRxFifoIsr(void)
{
    Uint16 i;
    for(i=0;i<2;i++)
    {
       rdataA[i]=ScibRegs.SCIRXBUF.all;  // Read data
    }
    for(i=0;i<2;i++)                     // Check received data
    {
       if(rdataA[i] != ( (rdata_pointA+i) & 0x00FF) ) error();
    }
    rdata_pointA = (rdata_pointA+1) & 0x00FF;

    ScibRegs.SCIFFRX.bit.RXFFOVRCLR=1;   // Clear Overflow flag
    ScibRegs.SCIFFRX.bit.RXFFINTCLR=1;   // Clear Interrupt flag

    PieCtrlRegs.PIEACK.all|=0x100;       // Issue PIE ack
}

void Scib_fifo_init()
{
   ScibRegs.SCICCR.all =0x0007;   // 1 stop bit,  No loopback
                                  // No parity,8 char bits,
                                  // async mode, idle-line protocol
   ScibRegs.SCICTL1.all =0x0003;  // enable TX, RX, internal SCICLK,
                                  // Disable RX ERR, SLEEP, TXWAKE
   ScibRegs.SCICTL2.bit.TXINTENA =1;
   ScibRegs.SCICTL2.bit.RXBKINTENA =1;
   ScibRegs.SCIHBAUD = 0x0000;
   ScibRegs.SCILBAUD = SCI_PRD;
   ScibRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back
   ScibRegs.SCIFFTX.all=0xC022;
   ScibRegs.SCIFFRX.all=0x0022;
   ScibRegs.SCIFFCT.all=0x00;

   ScibRegs.SCICTL1.all =0x0023;     // Relinquish SCI from Reset
   ScibRegs.SCIFFTX.bit.TXFIFOXRESET=1;
   ScibRegs.SCIFFRX.bit.RXFIFORESET=1;

}

//===========================================================================
// No more.
//===========================================================================

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    Expert 1590 points

    because I don't use loopback and only one char interrupt，so I modify your code and download .

    unfortunately, no interrupt is occurring just like my old code.

    Can you share me the demo code :

    1:SCIB single char interrupt, no fifo used or fifi trigger level is 1 char.

    2: no internal loopback testing mode.  

    // Initialize SCI/B:


    ScibRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
    // No parity,8 char bits,
    // async mode, idle-line protocol

    ScibRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
    // Disable RX ERR, SLEEP, TXWAKE
    ScibRegs.SCICTL2.bit.TXINTENA =0;
    ScibRegs.SCICTL2.bit.RXBKINTENA =1;

    ScibRegs.SCIHBAUD = BAUDRATE[3].SCIHB; //9600
    ScibRegs.SCILBAUD = BAUDRATE[3].SCILB; //9600
    // ScibRegs.SCICCR.bit.LOOPBKENA =0; // disable loop back

    // ScibRegs.SCIFFTX.bit.SCIFFENA = 0;
    // ScibRegs.SCIFFTX.bit.TXFFIENA = 0;
    // ScibRegs.SCIFFTX.bit.TXFFINT = 0;
    // ScibRegs.SCIFFTX.bit.SCIRST = 0;
    // ScibRegs.SCIFFTX.all=0xE040;//enable RX,FIFO !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! important
    ScibRegs.SCIFFTX.all = 0xc021;
    //no FIFO INT, clear TXFIFINT
    // ScibRegs.SCIFFRX.all=0x2021;
    ScibRegs.SCIFFRX.all=0x0021;
    ;

    ScibRegs.SCIFFCT.all=0x00;

    ScibRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
    ScibRegs.SCIFFTX.bit.TXFIFOXRESET=1;
    ScibRegs.SCIFFRX.bit.RXFIFORESET=1;

  • 0 in reply to decai wang
    Guru 13185 points

    Hello,

    Just want to make sure.

    Is your SCIB connected to RS232 transceiver or something similar? And is it the same chip for SCIA?

    Maybe this is hardware problem?

    Best regards,

    Maria

  • 0 in reply to decai wang
    Guru 13185 points

    Hello again,

    My SCI initialization is just like this (works well in F28069M):


        ScibRegs.SCICCR.all =0x0007;   // 1 stop bit,  No loopback
                                       // No parity,8 char bits,
                                       // async mode, idle-line protocol
        ScibRegs.SCICTL1.all =0x0003;  // enable TX, RX, internal SCICLK,
                                       // Disable RX ERR, SLEEP, TXWAKE
        
        ScibRegs.SCICTL2.bit.TXINTENA = 0;
        ScibRegs.SCICTL2.bit.RXBKINTENA = 1;

        
        ScibRegs.SCIHBAUD    =0x0001;  // 9600 baud @LSPCLK = 20MHz (80 MHz SYSCLK).
        ScibRegs.SCILBAUD    =0x0003;


        ScibRegs.SCICTL1.all =0x0023;  // Relinquish SCI from Reset

    No need FFTX, FFRX, and FIFORESET.

    If this doesn't work, please check your hardware.

    Best regards,

    Maria