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Quick ADC questions on F28M35

Michael He
Expert 2170 points

I'm working on the Concerto F28M35x and have some quick questions about the ADC modules, mostly making sure my understanding is correct.

1. Am I correct that SOCs can be triggered basically by the ADC Triggers or ADC Interrupts?
ADCSOC(x)CTL.bit.TRIGSEL = trigger; to choose a trigger, and
ADCINTSOCSEL1.bit.SOC1 = interrupt 1 or 2, which overrides the previous line for the same SOC

2. The second line above, setting an interrupt, only allows interrupt 1 or 2. However, in the documentation, there are interrupts up to 10 (INTSEL9N10). These cannot be used to trigger SOCs? Are they only for interrupt handlers?

3. The ADC Triggers are set by the register AnalogSysctrlRegs, while the ADC Interrupts are set in the register Adc(x)Regs.INTSEL(x)N(y), so am I correct in thinking that the ADC Triggers are common to both ADC modules (ADC1 and ADC2), while there are a set of ADC Interrupts for each module?

4. Finally, if I want channels A6/B6 to sample after the EOC of Channel A0/B0 (which are on SOC0/1), is this the correct configuration?

Adc1Regs.ADCINTSOCSEL2.bit.SOC10 = INT1;
Adc2Regs.ADCINTSOCSEL2.bit.SOC10 = INT2;

Adc1Regs.INTSEL1N2.bit.INT1E = 1;
Adc1Regs.INTSEL1N2.bit.INT1CONT = 1;
Adc1Regs.INTSEL1N2.bit.INT1SEL = 1; // EOC 1 happens after Channel B0 in the pair A0/B0 finishes

Adc2Regs.INTSEL1N2.bit.INT1E = 1;
Adc2Regs.INTSEL1N2.bit.INT1CONT = 1;
Adc2Regs.INTSEL1N2.bit.INT1SEL = 1; // EOC 1 happens after Channel B0 in the pair A0/B0 finishes

Adc1Regs.ADCSOC8CTL.bit.ACQPS = 6;
Adc1Regs.ADCSOC8CTL = // doesn't matter, overriden
Adc1Regs.ADCSOC8CTL.bit.CHSEL = 6; // For A6/B6

Adc2Regs.ADCSOC8CTL.bit.ACQPS = 6;
Adc2Regs.ADCSOC8CTL = // doesn't matter, overriden
Adc2Regs.ADCSOC8CTL.bit.CHSEL = 6; // For A6/B6

  • 0
    TI__Guru 62975 points

    Michael Hu. said:

    1. Am I correct that SOCs can be triggered basically by the ADC Triggers or ADC Interrupts?

    ADCSOC(x)CTL.bit.TRIGSEL = trigger; to choose a trigger, and
    ADCINTSOCSEL1.bit.SOC1 = interrupt 1 or 2, which overrides the previous line for the same SOC


    According to the TRM, yes.

    Michael Hu. said:

    2. The second line above, setting an interrupt, only allows interrupt 1 or 2. However, in the documentation, there are interrupts up to 10 (INTSEL9N10). These cannot be used to trigger SOCs? Are they only for interrupt handlers?


    Yes, only ADCINT1 and ADCINT2 can be used for SOC triggering. The others are for system level signaling/handling.

    Michael Hu. said:

    3. The ADC Triggers are set by the register AnalogSysctrlRegs, while the ADC Interrupts are set in the register Adc(x)Regs.INTSEL(x)N(y), so am I correct in thinking that the ADC Triggers are common to both ADC modules (ADC1 and ADC2), while there are a set of ADC Interrupts for each module?


    Yes, the available trigger sources determined by the AnalogSysCtrlRegs structure are the same for both ADCs, but each ADC/SOC can choose which trigger to use.

    Michael Hu. said:

    4. Finally, if I want channels A6/B6 to sample after the EOC of Channel A0/B0 (which are on SOC0/1), is this the correct configuration?


    It looks like you are trying to run the same configuration for both ADCs? If so, ADC2 ADCINTSOCSEL should be set to INT1 as well. I don't see the ADCINTSOCSEL configuration for SOC8 so I can't comment on how A6/B6 would be triggered.

  • 0 in reply to tlee
    Expert 2170 points

    Thank you.

    Yes, I have some typos there because I copied it over from two similar pieces. I do have ADC2 ADCINTSOCSEL set to INT1, and it actually should be SOC8 in the code I copied. I have exactly analogous code for SOC10 and Channels A7/B7, I just mixed the code when copying.

    So the basic structure is correct?

  • 0 in reply to Michael He
    TI__Guru 62975 points

    Sure. Typos aside, it looks reasonable.

  • 0 in reply to tlee
    Expert 2170 points

    It seems that my thinking on #3 was not entirely correct. From the reference manual, "There are a total of 8 interrupts available for both ADC1 and ADC2. Each ADC does not have its own set of 8 interrupts. These resources must be shared."

    It's weird then that there are registers for configuring the interrupts from both Adc1Regs and Adc2Regs.

  • 0 in reply to Michael He
    Expert 2170 points

    Can I ask an additional question?

    If I have an ADC1 SOC and an ADC2 SOC triggering off the same event, are they guaranteed to finish at the same time?
    The reason I ask is that there are a limited number of ADC interrupts between the two modules, so I have to share them. If I have an interrupt linked to ADC1 EOC1, for example, can I be guaranteed that ADC2 will also have finished conversion and have a valid value within the Interrupt Service Routine, given that they both started off the same trigger?

    Also, if I use an ADC Interrupt to trigger an SOC, I can still attach an ISR to that interrupt, right?

  • 0 in reply to Michael He
    TI__Guru 62975 points

    Michael Hu. said:
    It's weird then that there are registers for configuring the interrupts from both Adc1Regs and Adc2Regs.


    The interrupts are generated by the individual ADC modules and then combined together at a higher level.

    Michael Hu. said:
    If I have an ADC1 SOC and an ADC2 SOC triggering off the same event, are they guaranteed to finish at the same time?


    Yes, if you use the exact same trigger and configure the SOCs to have the same ACQPS, they should finish in the same cycle.

    Michael Hu. said:
    Also, if I use an ADC Interrupt to trigger an SOC, I can still attach an ISR to that interrupt, right?


    Yes, that interrupt signal is still dispatched to the rest of the system.

  • 0 in reply to tlee
    Expert 2170 points

    Thanks very much for all your help! I've got more questions popping up.

    I have two SOCs both triggering off the same ADC Trigger. I understand that they will follow the round-robin priority scheme in the technical reference manual to determine who goes first. My question is about timing. Looking at Figure 11-43, it looks like there is a delay of 19 ADC clock cycles between the sample and hold of the first SOC and the sample and hold of the second SOC. Is this correct? Is this the same delay that happens if I have two SOCs triggering together, following the round-robin priority scheme?

    Also, I assume that the timing example in this figure (11-43) requires NoOverlapMode to be OFF, correct?

  • 0 in reply to Michael He
    TI__Guru 62975 points

    Michael Hu. said:
    Looking at Figure 11-43, it looks like there is a delay of 19 ADC clock cycles between the sample and hold of the first SOC and the sample and hold of the second SOC. Is this correct? Is this the same delay that happens if I have two SOCs triggering together, following the round-robin priority scheme?

    Yes, 19 ADC cycles is the amount of time between the end of the ACQPS window for the first pair of channels to the start of the ACQPS window for the next pair of channels when multiple SOCs are pending in simultaneous mode.

    Michael Hu. said:
    Also, I assume that the timing example in this figure (11-43) requires NoOverlapMode to be OFF, correct?

    Yes, this requires that NoOverlapMode be OFF.