This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
I am designing my own PCB with the TMS320F28035. For my system to run without JTAG, do I need to pull GPIO34 and GPIO37 up to 3.3 volts to boot to FLASH on power up?
I plan to pull these pins high via a 2K resistor. Just want to verify this is what I need to do.
Gary,
Yes, that is a correct way to boot to FLASH on power up with the emulator disconnected.
If your emulator is not connected, when you pull GPIO34 and 37 high, you will boot to flash by default (assuming you did not program OTP_KEY and OTP_BMODE locations - 0x3d7bfe and 0x3d7bff, respectively with the boot values of any other boot mode).
Or, you can program OTP_KEY with 0x55AA, and OTP_BMODE with 0x000B - then with GPIO34 and 37 pulled high, the device will also boot to flash via the GetMode boot mode.
Thanks that helps.
I have another TMS320F28035 question. I am trying to compile some software for the 28035 and am getting an error with CCS 3.3. I have been trying CCS 4, but had to many problems and reverted back to CCS 3.3. Anyway, When I compile I get the following error when the software tries load.
Data Verification failed at address 0x3F6F90.
Please verify target memory and memory map.
Below is the cmd file that came with the motor control software I am using. It seems that 0x3F6F90 is a legal Flash location.
Do I have somthing wrong or could I have a bad 28035 part.
The part has been running fine when I load into RAM only, but I want to run stand alone , so I need to load into Flash.
Also, how do I attach files to a post?
/*==================================================================================*/
/* User specific Linker command file for running from FLASH */
/*==================================================================================*/
/* FILE: F28035_FLASH_2xPM_Motors.CMD */
/* */
/* Description: Linker command file for User custom sections targetted to run */
/* from FLASH. */
/* */
/* Target: TMS320F28035 */
/* */
/* Version: 1.00 */
/* */
/*----------------------------------------------------------------------------------*/
/* Copyright Texas Instruments © 2009 */
/*----------------------------------------------------------------------------------*/
/* Revision History: */
/*----------------------------------------------------------------------------------*/
/* Date | Description */
/*----------------------------------------------------------------------------------*/
/* 4/13/09 | Release 1.0 New release. */
/*----------------------------------------------------------------------------------*/
/* Define the memory block start/length for the F28035
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F2803x are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0 memory block is mirrored - that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks or flash sectors can be
be combined if required to create a larger memory block.
*/
MEMORY
{
/* Note that the memory allocation below does not create sections as necessary for
the CLA on the F2803x. Please download the Peripheral Files and Example Projects
collection (SPRC832) and look at the cla_adc project for information on how to
define sections for the CLA.
*/
PAGE 0:
progRAM : origin = 0x008000, length = 0x001000 /* on-chip RAM (L0-L2)*/
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHH : origin = 0x3E8000, length = 0x002000 /* on-chip FLASH */
FLASHG : origin = 0x3EA000, length = 0x002000 /* on-chip FLASH */
FLASHF : origin = 0x3EC000, length = 0x002000 /* on-chip FLASH */
FLASHE : origin = 0x3EE000, length = 0x002000 /* on-chip FLASH */
FLASHD : origin = 0x3F0000, length = 0x002000 /* on-chip FLASH */
FLASHC : origin = 0x3F2000, length = 0x002000 /* on-chip FLASH */
FLASHA : origin = 0x3F6000, length = 0x001F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
BOOTROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 :
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
dataRAM : origin = 0x009000, length = 0x001000 /* data RAM (L3) */
FLASHB : origin = 0x3F4000, length = 0x002000 /* on-chip FLASH */
CLA_CPU_MSGRAM : origin = 0x001480, length = 0x000080 /* CLA-R/W, CPU-R message RAM */
CPU_CLA_MSGRAM : origin = 0x001500, length = 0x000080 /* CPU-R/W, CLA-R message RAM */
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA, PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA, PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHD,
RUN = progRAM,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0, PAGE = 1
.ebss : > dataRAM, PAGE = 1
.esysmem : > dataRAM, PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHA PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES PAGE = 0, TYPE = NOLOAD /* Math Tables In ROM */
Cla1ToCpuMsgRAM : > CLA_CPU_MSGRAM PAGE = 1
CpuToCla1MsgRAM : > CPU_CLA_MSGRAM PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
}
SECTIONS
{
Net_terminals: > dataRAM,PAGE = 1
}
Gary,
I am guessing that this error occurs as you are trying to load the program. In order to load a flash program in CCSv3.3 you need to run the on-chip flash programmer after you have built a project. ("Tools->F28xx On-Chip Flash Programmer") Configure the clock timings for your system and then choose the .out file that should be flashed. Note, I would recommend you to leave all password locations as 0xFFFF until you go to production.
Note that in CCSv4, programming flash is done automatically when loading if it is needed.
Thank you,
Brett Larimore
