TMS320f28027 (master) && MSP430G2553 (slave) SPI

//###########################################################################
//
// Original Source by S.D.
//
// $TI Release: 2802x C/C++ Header Files V1.26 $
// $Release Date: February 2, 2010 $
//###########################################################################


#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File

// Prototype statements for functions found within this file.
// interrupt void ISRTimer2(void);
interrupt void spiTxFifoIsr(void);
interrupt void spiRxFifoIsr(void);
void delay_loop(void);
void spi_fifo_init(void);
void error();

unsigned char sdata[2];     // Send data buffer
unsigned char rdata[2];     // Receive data buffer
Uint16 rdata_point;  // Keep track of where we are
                     // in the data stream to check received data

void main(void)
 {
   Uint16 i;

   InitSysCtrl();

   InitSpiaGpio();


   DINT;
   IER = 0x0000;
   IFR = 0x0000;

   InitPieCtrl();

   InitPieVectTable();

   EALLOW;	// This is needed to write to EALLOW protected registers
   PieVectTable.SPIRXINTA = &spiRxFifoIsr;
   EDIS;   // This is needed to disable write to EALLOW protected registers

   spi_fifo_init();	  // Initialize the SPI only

   for(i=0; i<2; i++)
   {
      sdata[i] = i;
   }
   rdata_point = 0;


   PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   // Enable the PIE block
   PieCtrlRegs.PIEIER6.bit.INTx1=1;     // Enable PIE Group 6, INT 1
   IER=0x20;                            // Enable CPU INT6
   EINT;                                // Enable Global Interrupts


	for(;;)
	{
		 SpiaRegs.SPITXBUF=0;//sdata[0]<<8;      // Send data
		 sdata[0]++;
		 delay_loop();
	}

}

// Some Useful local functions
void delay_loop()
{
    long      i;
    for (i = 0; i < 10000; i++) {}
}

void error(void)
{
    asm("     ESTOP0");	 //Test failed!! Stop!
    for (;;);
}

void spi_fifo_init()
{
// Initialize SPI FIFO registers
   SpiaRegs.SPICCR.bit.SPISWRESET=0; // Reset SPI

   SpiaRegs.SPICCR.all=0x0007;       //16-bit character, Loopback mode
   SpiaRegs.SPICTL.all=0x0017;       //Interrupt enabled, Master/Slave XMIT enabled
   SpiaRegs.SPISTS.all=0x0000;
   SpiaRegs.SPIBRR=0x007d;           // Baud rate
 //  SpiaRegs.SPIFFTX.all=0xC022;      // Enable FIFO's, set TX FIFO level to 2
 //  SpiaRegs.SPIFFRX.all=0x0022;      // Set RX FIFO level to 2
   SpiaRegs.SPIFFCT.all=0x00;
   SpiaRegs.SPIPRI.all=0x0010;

   SpiaRegs.SPICCR.bit.SPISWRESET=1;  // Enable SPI

   SpiaRegs.SPIFFTX.bit.TXFIFO=1;
   SpiaRegs.SPIFFRX.bit.RXFIFORESET=1;
}

interrupt void spiRxFifoIsr(void)
{
    Uint16 i;

	rdata[0]=SpiaRegs.SPIRXBUF;		// Read data

	rdata_point++;
	SpiaRegs.SPIFFRX.bit.RXFFOVFCLR=1;  // Clear Overflow flag
	SpiaRegs.SPIFFRX.bit.RXFFINTCLR=1; 	// Clear Interrupt flag
	PieCtrlRegs.PIEACK.all|=0x20;       // Issue PIE ack
}

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#include <msp430.h>

unsigned char gauti1=0;
unsigned int i=0;

int main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop watchdog timer
  while (!(P1IN & BIT4));                   // If clock sig from mstr stays low,
                                            // it is not yet in SPI mode
  P1SEL = BIT1 + BIT2 + BIT4 + BIT5;
  P1SEL2 = BIT1 + BIT2 + BIT4 + BIT5;
  UCA0CTL1 = UCSWRST;                       // **Put state machine in reset**
  UCA0CTL0 |=  UCSYNC+  UCMSB + UCMODE1;
  UCA0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
  IE2 |= UCA0RXIE;                          // Enable USCI0 RX interrupt

  __bis_SR_register(LPM4_bits + GIE);       // Enter LPM4, enable interrupts
}

// Echo character
#pragma vector=USCIAB0RX_VECTOR
__interrupt void USCI0RX_ISR (void)
{
	i++;

	while (!(IFG2 & UCA0TXIFG));              // USCI_A0 TX buffer ready?

	UCA0TXBUF=0xff;

	switch (i) {
	  case 1:
		  UCA0TXBUF=0xf0;
	 break;
	  case 2:
		  UCA0TXBUF=0xff;

	  break;
	  case 3:
		  UCA0TXBUF=0xab;

      break;
	  case 4:
		  UCA0TXBUF=0xcd;
		  i=0;
	  break;
	  default: i=0; break;
	}
}