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28335 Tripzone

Isaac Pilli1
Intellectual 310 points

Hi,

Our PWM in 28335 is used to trigger ADC conversions and this drives the scheduler, other words all the product activity is derived off the PWM and its time-base counters. An added feature had been implemented: a Trip-Zone pin which is halting PWM outputs once an over -current is sensed. Whenever this TZ pin is activated - the associated PWM outputs are disabled and a TZ interrupt is fired.

This works well. However, it had been found that the scheduler is actually halted once the TZ pin is active. Shouldn't TZ input pin only affect the PWM outputs and *not* the internal Time-Base counters?

Thanks for looking, Isaac

============================================

The way TZ had been implemented is:

EALLOW;


// Configure GPIO14 as as TZ3
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0x0; // Enable pull-up on GPIO14 (TZ3)
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 0x1 ; // Configure GPIO14 as TZ3

// Configure EPWM modules to drive the axis 1 outputs off when TZ3 occurs
EPwm1Regs.TZSEL.bit.OSHT3 = TZ_ENABLE;
EPwm2Regs.TZSEL.bit.OSHT3 = TZ_ENABLE;
EPwm3Regs.TZSEL.bit.OSHT3 = TZ_ENABLE;

EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_LO;

// Configure TZ3 Interrupt
EPwm3Regs.TZEINT.bit.OST = 1; // Enables TZ interupt event
EPwm3Regs.TZCLR.bit.OST = 1; // Clears TZ Pending event
PieCtrlRegs.PIEIFR2.bit.INTx3 = 0;
EPwm3Regs.TZEINT.bit.OST = 1; // Enables TZ interupt event
PieCtrlRegs.PIEIER2.bit.INTx3 = 1;

EDIS;

  • 0
    Guru 192875 points

    Hi Isaac,

    Why don't you use a different PWM module for ADC conversions?

    For eg.

    Actual PWM -> PWM1

    PWM for ADC -> PWM2

    Because, when a one shot type trip zone is triggered the respective PWM would be totally switched off with its TBCTR. This will halt all your ADC conversions.

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    Intellectual 310 points

    Thanks Gautam,

    In this application TZ3 requires to trip PWM1,2,3 - a total of 6 output pins.Also required that ADC would be synchronise with these PWM's.

    Two solutions had been considered:

    (1) The solution you've proposed but according to ADC Reference guide ( SPRUG04A.pdf)  Figure 9 (attached)7180.PWM_sprug04a.pdf- it seem that once TZ3 is activated and trips PWM1,2,3 - then PWM4,5,6 would also lose their PWM source as all is derived from PWM1. Is this understanding correct?

    (2) I activated NMI from GPIU14 (TZ3) and from within the interrupt made the 6 PWM's output pins disabled. However, to my surprise, it took hundreds of Micro Seconds for the pins to stop their PWM's ( WHY? ), much more than required.

    Any advice for any of the solutions or a new approach? Required to disable PWM's within few Micro Seconds.

    Isaac

  • 0 in reply to Isaac Pilli1
    Guru 192875 points

    Hi Isaac,

    Why don't you configure individual trip zones for their respective EPWMs? If you want TZ3 to trip all 3 ePWMs 1,2,3 then short these TZ signals ie TZ1,2,3. In this way ePWM4,5,6 would be unaffected.

    Also, you can try using external interrupts XINT0 for turning your ePWM signals off and the delay over here is minimal.

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    Intellectual 310 points

    Gautam,

    This might have been possible with new hardware design but the hardware platform is already done. In the existing platform, based on the above mentioned figure 9 - if ADC needs to be sync with PWM1,2,3 and PWM1 needs to be tripped - then even if one of the PWM4,5,6 is driving the ADC -  then the whole tree, including PWM4,5,6 would be halted as it is all derived from PWM1.

    Back to the the second solution:  I tried an external interrupt and from the time this code was running ... 

    EALLOW;

    GpioDataRegs.GPASET.all |= 0x0000003F; // GPIO0 through GPIO5 driven high
    GpioCtrlRegs.GPADIR.all |= 0x0000003F; // GPIO0 through GPIO5 as outputs
    GpioCtrlRegs.GPAMUX1.all &= ~0x00000555; // GPIO0 through GPIO5 as GPIO

    EDIS;

    ... it lasts hundreds of micro seconds till the 6 PWM signals actually halted. I was expecting more of nano-seconds sort of time. Nothing in the data sheet about the timing it should last.

    It seem to me that both solutions have a problem in them. Any idea?

    Isaac

  • 0 in reply to Isaac Pilli1
    Guru 192875 points

    if ADC needs to be sync with PWM1,2,3 and PWM1 needs to be tripped - then even if one of the PWM4,5,6 is driving the ADC -  then the whole tree, including PWM4,5,6 would be halted as it is all derived from PWM1.

    Yup, if we consider figure9 it does convey the above scenario.

    ... it lasts hundreds of micro seconds till the 6 PWM signals actually halted. I was expecting more of nano-seconds sort of time.

    Here it seems to be a priority issue esp. if timer interrupt is also present. You can check this link to prioritize your external interrupt accordintly: http://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x

    Regards,

    Gautam