F28027 SPI FIFO LEVEL problem

Hi,

I have a problem achieving an SPI transmit with FIFO level of 7 as a master on F28027. Basically, I want to send seven bytes in a row, because my SPI slave needs 1 byte with address and then 6 bytes of data to write to this address. I used PICCOLO SPI loopback example as a template to modify my code, but I'm getting only 5 bytes on SPISIMO. Modifying FIFO level doesn't take effect, it's always on 5 for some reason. I don't use interrupts and don't use RX. Here's the problematic code:

void delay_loop(void);
void spi_fifo_init(void);

void main(void)
{

typedef struct {
Uint16 Txdata1;
Uint16 Txdata2;
Uint16 Txdata3;
Uint16 Txdata4;
Uint16 Txdata5;
Uint16 Txdata6;
Uint16 Txdata7;
} REG1;

REG1 REG01;

REG01.Txdata1 = 0x07;
REG01.Txdata2 = 0x10;
REG01.Txdata3 = 0x24;
REG01.Txdata4 = 0x01;
REG01.Txdata5 = 0x01;
REG01.Txdata6 = 0x00;
REG01.Txdata7 = 0x00;

   InitSysCtrl();

   InitSpiaGpio();

   DINT;

   InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;

   InitPieVectTable();

   spi_fifo_init();  // Initialize the Spi FIFO

SpiaRegs.SPITXBUF = REG01.Txdata1<<8; 
SpiaRegs.SPITXBUF = REG01.Txdata2<<8; 
SpiaRegs.SPITXBUF = REG01.Txdata3<<8;
SpiaRegs.SPITXBUF = REG01.Txdata4<<8;
SpiaRegs.SPITXBUF = REG01.Txdata5<<8;
SpiaRegs.SPITXBUF = REG01.Txdata6<<8;
SpiaRegs.SPITXBUF = REG01.Txdata7<<8;

delay_loop();

}

void delay_loop()
{
long i;
for (i = 0; i < 35000; i++) {} //10000000
}

void spi_fifo_init()
{
// Initialize SPI FIFO registers
// SpiaRegs.SPIFFTX.bit.SPIRST = 1;
// SpiaRegs.SPIFFTX.bit.SPIFFENA = 1; // enable fifo enhancements
// SpiaRegs.SPIFFTX.bit.TXFIFO = 1; // re-enable tx fifo

SpiaRegs.SPICCR.all=0x0007; //8-bit
SpiaRegs.SPIFFTX.all=0xC006; // Enable FIFO's, set TX FIFO level to 7
SpiaRegs.SPICTL.all=0x0006; //Interrupt enabled, Master/Slave XMIT enabled -17
SpiaRegs.SPISTS.all=0x0000;
SpiaRegs.SPIBRR=0x0063; // Baud rate
SpiaRegs.SPIFFCT.all=0x00; // No time delay between packets
SpiaRegs.SPIPRI.all=0x0010; //Priority control - transmit until FIFOTX empty
SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SPI

SpiaRegs.SPIFFTX.bit.TXFIFO=1;

}