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Powerup glitch on GPIO in F28069

Naresh Desai
Intellectual 355 points

Hello,

We are using with F28069.

When we powerup the device, there is a glitch of 1v for 50ms on  GPIO51.

we have use the first instruction within the main() to disabling the internal pull-up resister.

we have also 4.7k pulldown resister externally on gpio.

Is there any way to disabling the internal pull-up resister on a F28069.

Regards,

Naresh

  • 0
    Guru 192875 points

    Hi Naresh,

    Is there any way to disabling the internal pull-up resister on a F28069.

    This register is EALLOW protected, so I hope you're using EALOW; before initializing the same.

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    Intellectual 355 points

    yes, I have using EALLOW before init gpio.

    I have notice that this glitch is occurs before calling main() function.

    when powerup the device, GPIO51  pull high untill main() is called.  After calling main, GPIO51 goes to low as I have disabling pullup in main().

    I know default state of GPIO51 is pullup.

    I want to pulldown GPIO line from powerup.

    Is there any workaround to remove this powerup glitch?

    Regards

    Naresh.

  • 0 in reply to Naresh Desai
    Guru 192875 points

    Hi Naresh,

    Are you by any chance using Trip zones?

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    Intellectual 355 points

    Thanks Gautam,

    I have used PWM and trip zones for other purpose in my design. and at this stage, Hardware modification is not possible for me.

    Is there any solution in firmware to remove this glitch?

    Regards,

    Naresh

  • 0 in reply to Naresh Desai
    Guru 192875 points

    Naresh, GPIO51 also represent TZ2. So if,  you're initializing  InitTzGpio(); function then you've to comment TZ2 initializations found in the same function to eliminate the above error.

    Let me know what you observe.

    Regards,

    Gautam

  • 0
    Prodigy 80 points

    I don't think you will be able to fix this problem in software. It sounds like the glitch is just the normal default hardware state as the F28069 powers up and before your code starts to execute. You can't disable the internal pull-up until your code starts.

    Reducing the value of your pull-down resistor will limit the glitch voltage and could prevent it causing a problem. In this situation I usually use 2k2 which holds the GPIO at logic 0 for most 3V logic devices at power up.