• State Answer Suggested
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 81 subscribers
  • Views 400 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

I2C FIFO & NACK

Lukas Sk
Intellectual 305 points

Hi,

    I have problem with I2C module that I do not know how to distinguish NACK interrupt from last Tx byte and NACK interrupt form not last Tx byte when using FIFO. So I am not able to distinguish between correct and incorrrect I2C transfer.
    Here is similar thread with no reactions when using pooling: http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/286328.aspx.
     Is it even possible to correctly use NACK interrupt and FIFO together?

  • 0
    Intellectual 305 points

    Well I think that I have found solution.
        It looks like that after NACK interrupt I2C transmission is terminated and no data is shifted out from Tx FIFO. So I can check TXFFST=0 to determine if it is NACK interrupt from last byte. But I haven't found anything in documentation to support this theory.