This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

F28335 Flash Optimization



I'm working with a SYS/BIOS project that runs from flash. To speed up operation I'm a flash optimization routine. Most of the flash register settings work as expected. I run into an issue with PAGEWAIT and ENPIPE.

We are using a clock rate of 144MHz. With this clock rate decreasing the PAGEWAIT below the default or enabling the pipeline causes the code to jump to an unexpected locations. After the jump, all instructions in the disassembly window appear as ITRAP0's.

We are using CCSv5.5.0.00077 with SYS/BIOS version 6.35.4.50.

The following is our flash initialization in the "good" state:

#pragma CODE_SECTION(InitFlash, "SecureRamFuncs")
void InitFlash(void)
{
    EALLOW;

    FlashRegs.FPWR.bit.PWR = 3;
    FlashRegs.FSTATUS.bit.V3STAT = 1;
    FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
    FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
    FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;
    FlashRegs.FBANKWAIT.bit.PAGEWAIT = 15;   // If this is less than 15 the code behaves unpredictably.
    FlashRegs.FOTPWAIT.bit.OTPWAIT = 8;
    FlashRegs.FOPT.bit.ENPIPE = 0;   // If this is 1 the code behaves unpredictably.

    EDIS;

    NOP10;
}    // End void InitFlash(void)

SecureRamFuncs are loaded into L03SARAM. A memcpy is used to transfer the code from flash into RAM. The registers are changing as expected.

Thank you for your help.