Hi,
In the data sheet for SM320F28335-HT it is stated that:
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for tw(RSL1) after the input clock is stable (see Table 6-
10). This is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8 µs prior to VDD reaching 1.5 V. This is to
enhance flash reliability.
My questions are as follows:
1. What is the consequence of violating requirement 2? What is meant by enhancing flash relability when conforming to this requirement?
2. Is there any feasible way to avoid violating this when the system is shutting down? Our system is typically shut down when the user is removing the input voltage (without any other "warning" to the system). Luckily the input voltage for the system is significantly higher than the microcontroller voltage. Therefore we can detect when the input voltage gets below a certain threshold and take care then (assuming there is enough time to maintain stable 3.3 V and 1.9 V for the microcontroller). Is there any (high temperature > 150 deg. C) solution reference circuit/brownout detection IC that can trigger on both rising and falling input voltage and hold the CPU in reset according to these recommendations?
