Hi E2E-ers,
I'm having two custom PCB boards (one development board and one final board) and on both I'm using TMS320F28334 XINTF0 interface for reading out a 32bit external peripheral.
The strange thing is:
On the development board I'm able to read out XINTF0 data and I see xRD pin and address pins changing while read. But with the same project on the 'final' board it's not working!? Meaning I don't read data, pins are not changing. When I read with DMA, them DMA stalls (not counting DST and SRC registers).
I'm not using the "READY" option..
My XINTF configuration is:
void XintfInit(void)
{ /*Check for configurations conflicts using XINTFENCLK*/
if( SysCtrlRegs.PCLKCR3.bit.XINTFENCLK == TRUE ) asm(" ESTOP0");
EALLOW;
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = TRUE;
// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = 1x SYSCLKOUT
asm(" RPT #7 || NOP; ");
XintfRegs.XINTCNF2.bit.XTIMCLK = 0;
// No write buffering
XintfRegs.XINTCNF2.bit.WRBUFF = 0;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// XCLKOUT = XTIMCLK
XintfRegs.XINTCNF2.bit.CLKMODE = 0;
// Zone 0------------------------------------
/* Source clock is 1/2 systemclock, so 75MHz (13,33ns CLK cycle)
* 1 Xintf Read = 1Lead + (1+1)Active = 2CLK cycles = 40ns.
* 1DMA period = 4 DMA reads = 4x40ns + 1DMAQ 'reset' = 173.33ns
* 1 period = 33.333uS, so 1 period = 192 reads max, or 48 DMA periods each containing 4 reads.
*/
XintfRegs.XTIMING0.bit.XWRLEAD = 1; //keep idle for n clockcycles
XintfRegs.XTIMING0.bit.XWRACTIVE = 1; //active for n clockcycles
XintfRegs.XTIMING0.bit.XWRTRAIL = 0; //keep idle for n clockcycles
// Zone read timing
XintfRegs.XTIMING0.bit.XRDLEAD = 1;
XintfRegs.XTIMING0.bit.XRDACTIVE = 1; //might be two to get lower clock duty cycle.
XintfRegs.XTIMING0.bit.XRDTRAIL = 0;
// NOT double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING0.bit.X2TIMING = 0;
// Zone will NOT sample XREADY signal
XintfRegs.XTIMING0.bit.USEREADY = 0;
XintfRegs.XTIMING0.bit.READYMODE = 0; //
// Size must be either 0,1 or 3:
XintfRegs.XTIMING0.bit.XSIZE = 1; // 0,1 = x32 or
// Zone 6------------------------------------
// Zone write timing
XintfRegs.XTIMING6.bit.XWRLEAD = 3;
XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING6.bit.XRDLEAD = 3;
XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
// NOT double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING6.bit.X2TIMING = 0;
// Zone will NOT sample XREADY signal
XintfRegs.XTIMING6.bit.USEREADY = 0;
XintfRegs.XTIMING6.bit.READYMODE = 0; // sample asynchronous
// Size must be either 0,1 or 3:
XintfRegs.XTIMING6.bit.XSIZE = 1; // 0,1 = x32 or
// Zone 7------------------------------------
// Zone write timing
XintfRegs.XTIMING7.bit.XWRLEAD = 3;
XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING7.bit.XRDLEAD = 3;
XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING7.bit.X2TIMING = 1;
// Zone will NOT sample XREADY signal
XintfRegs.XTIMING7.bit.USEREADY = 0;
XintfRegs.XTIMING7.bit.READYMODE = 0; // sample asynchronous
// Size must be either 0,1 or 3:
XintfRegs.XTIMING7.bit.XSIZE = 1; // 0,1 = x32 or
// Bank switching
XintfRegs.XBANK.bit.BANK = 7;
XintfRegs.XBANK.bit.BCYC = 7;
EDIS;
InitXintf16Gpio();
InitXintf32Gpio();
asm(" RPT #7 || NOP");
}
Best regards,
Tjar
