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Two f28335 Communication through SCI (FIFO enabled) does not work on full duplex

Favian Estrada
Prodigy 20 points

I have two F28335 communication with each other through SCI, with FIFO enabled. The code inputs 8 bytes into the TX FIFO and waits for the Interrupt to input again.

I hooked up the O-scope and noticed that when the messages overlap one of the processors does not receive any messages and the RX EMU buffer stays empty. It works perfectly when they do not overlap.

I am wondering if this behavior is intended and over lapping should be avoided, or am I missing something that would allow me to have over lapping in messages.  Ideas on what would cause this behavior would be appreciated as well.

Thank you,
Favian

  • 0
    Prodigy 20 points

    I figured it out. Over lapping does not matter. The problem came from starting up the processors at different time. The first one would Init the GPIOs and then set the SCI Regs, when it would get to the RXENA portion it would see that the RX input is still low because it has not been INIT yet by the other processor so it was detecting a false start.

  • 0 in reply to Favian Estrada
    Intellectual 450 points

    Are you willing to share your code as i am trying to accomplish the same thing?


    Thanks,