I'm trying to use the ecap modules to detect rising and falling edges and zeroing them out by adjusting frequency so that I can run my system "in phase"
ECap1 is my voltage signal
ECap2 is my current signal
I'm trying to line up the rising edge of the voltage with the falling edge of the current by adjusting the frequency. For the most part my code is working but occasionally my "phase" value will jump from what I would expect to be getting when I'm totally off phase to what seems like a random number and that can significantly through off the calculation. Attached is a picture of the two signals going to the ECaps.
Here is the ECap setup routing
void Setup_eCAP(void)
{
ECap1Regs.ECCTL1.bit.CAP1POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP2POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP3POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP4POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CTRRST1 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CTRRST2 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CTRRST3 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CTRRST4 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CAPLDEN = EC_ENABLE;
ECap1Regs.ECCTL1.bit.PRESCALE = EC_DIV1;
ECap1Regs.ECCTL1.bit.FREE_SOFT = 2;
ECap1Regs.ECCTL2.bit.CONT_ONESHT = EC_ONESHT;
ECap1Regs.ECCTL2.bit.SWSYNC = 1;
ECap1Regs.ECCTL2.bit.SYNCO_SEL = 00;
ECap1Regs.ECCTL2.bit.SYNCI_EN = EC_ENABLE;
ECap1Regs.ECCTL2.bit.TSCTRSTOP = EC_RUN;
ECap2Regs.ECCTL1.bit.CAP1POL = EC_FALLING;
ECap2Regs.ECCTL1.bit.CAP2POL = EC_FALLING;
ECap2Regs.ECCTL1.bit.CAP3POL = EC_FALLING;
ECap2Regs.ECCTL1.bit.CAP4POL = EC_FALLING;
ECap2Regs.ECCTL1.bit.CTRRST1 = EC_ABS_MODE;
ECap2Regs.ECCTL1.bit.CTRRST2 = EC_ABS_MODE;
ECap2Regs.ECCTL1.bit.CTRRST3 = EC_ABS_MODE;
ECap2Regs.ECCTL1.bit.CTRRST4 = EC_ABS_MODE;
ECap2Regs.ECCTL1.bit.CAPLDEN = EC_ENABLE;
ECap2Regs.ECCTL1.bit.PRESCALE = EC_DIV1;
ECap2Regs.ECCTL1.bit.FREE_SOFT = 2;
ECap2Regs.ECCTL2.bit.CONT_ONESHT = EC_ONESHT;
ECap2Regs.ECCTL2.bit.SYNCO_SEL = 00;
ECap2Regs.ECCTL2.bit.SYNCI_EN = EC_ENABLE;
ECap2Regs.ECCTL2.bit.TSCTRSTOP = EC_RUN;
}
Here is the calculation of the phase inside timer0
if(ECap1Regs.ECFLG.bit.CEVT4&&ECap2Regs.ECFLG.bit.CEVT4&&ECap5Regs.ECFLG.bit.CEVT1)
{
V_rising_1 = ECap1Regs.CAP1;
V_rising_2 = ECap1Regs.CAP2;
V_rising_3 = ECap1Regs.CAP3;
V_rising_4 = ECap1Regs.CAP4;
I_falling_1 = ECap2Regs.CAP1;
I_falling_2 = ECap2Regs.CAP2;
I_falling_3 = ECap2Regs.CAP3;
I_falling_4 = ECap2Regs.CAP4;
phase1 = I_falling_1-V_rising_1;
phase2 = I_falling_2-V_rising_2;
phase3 = I_falling_3-V_rising_3;
phase4 = I_falling_4-V_rising_4;
phase = (phase1+phase2+phase3+phase4)/4;
frequency = 150000000/(ECap5Regs.CAP2-ECap5Regs.CAP1);
ECap2Regs.ECCLR.bit.CEVT4=1;
ECap2Regs.ECCTL2.bit.REARM=1;
ECap1Regs.ECCLR.bit.CEVT4=1;
ECap1Regs.ECCTL2.bit.REARM=1;
ECap5Regs.ECCTL2.bit.REARM=1;
NEW_CAP_VALS=1;
}
Here is the code inside the main while loop that moves the frequency based on the phase information
if (new_ad_vals&&NEW_CAP_VALS)
{
new_ad_vals=0;
NEW_CAP_VALS=0;
if(phase<-400&&DIG_FREQ_ePWM<HIGH_VCO)
{
DIG_FREQ_ePWM++;
//DELAY_US(2200);
}
else if (phase>0&&DIG_FREQ_ePWM>LOW_VCO)
{
DIG_FREQ_ePWM--;
//DELAY_US(2200);
}
}
If anyone has any suggestions I'm open to trying anything.