Designing sensors in InstaSPIN project

none of this is necessary. you can run into deep field weakening even w/o modulation > 1.15.

If you choose to do #2, just make sure the current is scaled +/- to the 3.3V - 0 V on ADC, check your bias direction for +/- current, and update your user.h ADC_CURRENT and IQ_CURRENT settings (and change current sensors to (2), you do not need to use the third.  No need to change the sample location, the default for all projects takes in the middle of the low-side active dutyc, not that it matters much for LEM.

#3. It's not really required, though nice to have.  We keep meaning to udpate our ADC driver to actually use the 2 S/H circuit...but as you can see performance is excellent w/o.  Would probably help some with the shunts, but even less necessary if you do use LEMs.

ok, thanks a lot Chris.

Just to be sure - Don't we need 3 current sensors for modulation > 1 ?

What about the functions used in lab10 - reconstruction etc ? do I need to run them ?

Mojo said:

Just to be sure - Don't we need 3 current sensors for modulation > 1 ?

Not if you are using in-line current sensors. 

Mojo said:

What about the functions used in lab10 - reconstruction etc ? do I need to run them ?

Not if you are using in-line current sensors.

Both of these topics, using a 3rd shunt and taking action to always choose best 2 of 3 samples, are only required when your current samples can not be measured due to low-side FET on-time being too small.  With phase current measurements you have no sampling limitation.

Hi Chris,

Another question regarding the voltage sensors:

Most of the motors I will use with instaSPIN run > 800 Hz.

When I design my own board, let's assume that I can get really accurate capacitors and that their cost is negligible to me, then from the FAST estimator point of view - would it be better to use higher frequency or lower frequency filters ?

From the excel sheet you provided, gamma version, there are 2 fields for the filters. When I input a motor with 1kHz speed, The "Ideal filter" says 550hz and half is 275 Hz. what would be preferred from the estimator point of view and total control system stability, considering also temperature drift etc?

Thanks a lot

There is a delta version of the spreadsheet, and I am about to upload an epsilon. Maybe I should change this to numbers...doubt the greek alphabet is known by many.

Use lower frequency filters.

It is best when possible to choose the voltage fitler poles to MAX_Hz + Buffer / 4.

That is what we show in the spreadsheet. For example, with a target of 1200 Hz the spreadsheet will recommend 330 Hz filter pole.

The /2 option is for VERY high frequency systems. For example, with a target of 2400 Hz, the spreadsheet will recommend a 660 Hz filter pole, which is more susceptible to drift (the DRV8312 EVM pole is already higher than this, which is not ideal).  IF you wanted to, you could instead design for half at 330 Hz but then you must follow the ** note: Set USER_IQ_FULL_SCALE_FREQ_HZ <= 4 * Lowered Pole  * 0.95 buffer. Target Hz can reach +/- 1.98 * USER_IQ_FULL_SCALE_FREQ_Hz

This takes advantage of the fact that the per unit speed/frequency variable is in IQ24 which allows -2.0 to 1.99 range. So you can command a speed/frequency nearly twice USER_IQ_FULL_SCALE_FREQ_HZ.  This should be very uncommon for most users though.

Ok, thanks

Does what you suggest also apply when working at modulation index > 1.15 ?

Don't you loose valuable information (third harmonic etc) of the modulation by using MAX_SPEED/4 filter poles ?

I'm designing now my own HW based on the 69M, so all these questions rise...

Thanks

IQ_FULL_SCALE / FILTER_POLE < 4

is the lower limit of the FILTER_POLE.

You can make the FILTER_POLE larger if you like, but that is where you start to run into issues with accuracy and drift of the capacitors matching on the three phase voltages.

With FAST it really isn't necessary for your filter to be larger than the frequency you are running due to the compensation we use internally.

I think you ment:

IQ_FULL_SCALE / FILTER_POLE < 4

good catch, corrected above.

Hi Chris,

I will be using a maximum dc bus of 32 volt

is it ok to set USER_ADC_FULL_SCALE_VOLTAGE_V to 36 ? i.e set the voltage dividers to a margin just above the dc bus

typically yes. You'll note on BOOSTXL that we have a 24V bus and use 26.314 for the ADC scaling.

Thanks a lot Chris.

Regarding the current sensors - could you please repeat the problem in the DRV8301 kit with the electronic design ?

If using in-phase current sensors, does the solution to the above applies ?

What about high-frequency filtering (i.e above PWM frequency, for some high freq. noise) ?

Thanks

Mojo,

I'm sorry, I don't follow any of your questions. Please clarify.

You once said that the design of the current sensing in the drv8301 kit is not the best - something about the output of the amplifier being too far away from the uC... or maybe I'm mistaken ?

Ahh yes, now I understand what you are asking.

On the DRV8301 EVM the output of the sensed current signals take long paths back to the ADC pin on the MCU.  They pick up noise and interfere with each other at high modulation.

 It is better to limit the path of the scaled 0-3.3V signal, so place it close as possible to the ADC pins (or the PGA input to the DRV8301). The BOOSTXL-DRV8301 design is good to follow for layout guidance.

"If using in-phase current sensors, does the solution to the above applies ?"

It is always a good idea to limit contamination of the signal, but not sure what could be done with a LEM / hall type sensor. 

"What about high-frequency filtering (i.e above PWM frequency, for some high freq. noise) ?"

No, we don't recommend.

Ok, thanks.

by the way, I just changed today the sense circuitry of the phase voltage sampling, changing to 36V full scale. However, I forgot to change the DC-bus dividers too... I think although this is obvious, it should be mentioned in the HW_UG. It'll be easier for people not to repeat that mistake.