C2000 SPI

Hi ,

I am using the F28027 processor and writing code using the register structure approach,I am developing code based on the example SPI_Loopback_Interrupts .....A few queries

1 >>I am using the SPI module in 16 bit mode and the issue is that even when i am writing a command to my SPI slave my rx buffer is constantly getting filled/reading

so if i send a 16-bit command  and then give a 0x0000 (providing clock for the slave) , my rx buffer's first word is junk data (mostly 0xFFFF/0x0000)  and only the next word is usable ,

How do i avoid this ?? Should i disable RX interrupt till i send the command ??

2>>I need to first configure my slave and then read an error register to check for errors , but in the example the data is sent in the TX_ISR ,and the controller is running the infinite loop ,sending data continuously 

How do i send data when i wish and then stop , i mean if i just need to send 2 words and then stop

I understand that the interrupt occurs when TXFFST < TXFFIL , So does the interrupt occur (if enabled) and there is something put in the buffer ??

3 >> How can i send data outside the TX_ISR ??

Here is the present configuration of the interrupt and SPI FIFO registers that i am using

main ()
{

InitPieVectTable();

// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.SPIRXINTA = &spiRxFifoIsr;
PieVectTable.SPITXINTA = &spiTxFifoIsr;
EDIS; // This is needed to disable write to EALLOW protected registers

// Step 4. Initialize the SPI Peripheral:
spi_fifo_init();

// Step 5. User specific code, enable interrupts:

// Initalize the send data buffer



// Enable interrupts required for this example
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER6.bit.INTx1=1; // Enable PIE Group 6, INT 1
PieCtrlRegs.PIEIER6.bit.INTx2=1; // Enable PIE Group 6, INT 2
IER=0x20; // Enable CPU INT6
EINT; // Enable Global Interrupts


}

void spi_fifo_init()
{
	// Initialize SPI FIFO registers
	SpiaRegs.SPICCR.bit.SPISWRESET=0;		// Reset SPI
	SpiaRegs.SPICCR.all= 0x000F;       		//16-bit character mode
	SpiaRegs.SPICTL.all=0x0007;	       		//Interrupt enabled, Master/Slave XMIT enabled
	SpiaRegs.SPISTS.all=0x0000;
	SpiaRegs.SPIBRR=0x0063;           		// Baud rate
	SpiaRegs.SPIFFTX.all=0xC022;       		// Enable FIFO's, set TX FIFO level to 2
	SpiaRegs.SPIFFRX.all=0x0022;      		// Set RX FIFO level to 2
	SpiaRegs.SPIFFCT.all=0x00;
	SpiaRegs.SPIPRI.all=0x0010;

	SpiaRegs.SPICCR.bit.SPISWRESET=1;  		// Enable SPI

	SpiaRegs.SPIFFTX.bit.TXFIFO=1;
	SpiaRegs.SPIFFRX.bit.RXFIFORESET=1;


	SpiaRegs.SPIFFTX.bit.TXFFINTCLR=1;  	// Clear Interrupt flag

}