Phase delaying ADC signal in TMS320F28069

Hello Divya

This TIVA Forum (TM4C). You would need to move it to C2000 Forum for TMS320 devices

Regards

Amit

Hi Divya,

I would like you to go through this link which has an attached project:

http://e2e.ti.com/group/launchyourdesign/m/c2000microcontrollerprojects/665489.aspx

Regards,

Gautam

Gautam

Thanks for your reply .But I could not find the code of the project mentioned in the link above.Project description tells about a PLL and delaying the sine by 90 degree.But this code i could not find.Below i am attatching my code, and highlighted the portion where i need to insert the code for delaying the sine wave.

Divya

// TI File $Revision: /main/2 $
// Checkin $Date: January 4, 2011 10:02:04 $
//###########################################################################
//
// FILE: Example_2806xCpuTimer.c
//
// Description:
//
// This example configures CPU Timer0, 1, and 2 and increments
// a counter each time the timer asserts an interrupt.
//
// Watch Variables:
// CpuTimer0.InterruptCount
// CpuTimer1.InterruptCount
// CpuTimer2.InterruptCount
//
//###########################################################################
// $TI Release: 2806x C/C++ Header Files and Peripheral Examples V1.00 $
// $Release Date: January 11, 2011 $
//###########################################################################
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include <math.h>
#define RED_delay=170;
#define FED_delay=170;
// Prototype statements for functions found within this file.
interrupt void cpu_timer0_isr(void);
interrupt void cpu_timer1_isr(void);
interrupt void cpu_timer2_isr(void);
// Prototype statements for functions found within this file.
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
Uint16 EPwm_CMPA_Direction;
Uint16 EPwm_CMPB_Direction;
Uint16 EPwmTimerIntCount;
Uint16 EPwmMaxCMPA;
Uint16 EPwmMinCMPA;
Uint16 EPwmMaxCMPB;
Uint16 EPwmMinCMPB;
// Configure the period for each timer
#define EPWM1_TIMER_TBPRD 6000 // Period register
#define EPWM1_MAX_CMPA 5950
#define EPWM1_MIN_CMPA 50
#define EPWM1_MAX_CMPB 5950
#define EPWM1_MIN_CMPB 50
#define EPWM2_TIMER_TBPRD 2000 // Period register
#define EPWM2_MAX_CMPA 1950
#define EPWM2_MIN_CMPA 50
#define EPWM2_MAX_CMPB 1950
#define EPWM2_MIN_CMPB 50
#define EPWM3_TIMER_TBPRD 2000 // Period register
#define EPWM3_MAX_CMPA 1950
#define EPWM3_MIN_CMPA 50
#define EPWM3_MAX_CMPB 1950
#define EPWM3_MIN_CMPB 50
// To keep track of which way the compare value is moving
#define EPWM_CMP_UP 1
#define EPWM_CMP_DOWN 0
void main(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2806x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initalize GPIO:
// This example function is found in the F2806x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
EALLOW;
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0; // GPIO18 = GPIO18
GpioCtrlRegs.GPADIR.bit.GPIO18 = 1; // GPIO18 = output ->1
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 0; // 0=GPIO,
GpioCtrlRegs.GPADIR.bit.GPIO16 = 1; // 1=OUTput, 0=INput
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // 0=GPIO,
GpioCtrlRegs.GPADIR.bit.GPIO19 = 1; // 1=OUTput, 0=INput
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0;
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO1 = epwm
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO1 = epwm
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO1 = epwm
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO1 = epwm
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // GPIO1 = epwm
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // GPIO1 = epwm
EDIS;
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // Enable ADC peripheral clock
(*Device_cal)(); // Auto-calibrate from TI OTP
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 0; // Return ADC clock to original state
EDIS;
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2806x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2806x_DefaultIsr.c.
// This function is found in F2806x_PieVect.c.
InitPieVectTable();
// For this example, only initialize the ePWM
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
//Configure ADC
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
AdcRegs.ADCCTL1.bit.ADCREFSEL = 0; // Use internal bandgap
AdcRegs.ADCCTL1.bit.ADCBGPWD = 1; // Power up band gap
AdcRegs.ADCCTL1.bit.ADCREFPWD = 1; // Power up reference
AdcRegs.ADCCTL1.bit.ADCPWDN = 1; // Power up rest of ADC
AdcRegs.ADCCTL1.bit.ADCENABLE = 1; // Enable ADC
for(i=0; i<5000; i++){} // wait 60000 cycles = 1ms (each iteration is 12 cycles)
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1; // create int pulses 1 cycle prior to output latch
//set S/H window to 6 clk cycles (112.5ns)
AdcRegs.ADCSOC0CTL.bit.ACQPS = 8;
AdcRegs.ADCSOC1CTL.bit.ACQPS = 8;
AdcRegs.ADCSOC2CTL.bit.ACQPS = 8;
AdcRegs.ADCSOC4CTL.bit.ACQPS = 8;
AdcRegs.ADCSOC5CTL.bit.ACQPS = 8;
AdcRegs.ADCSOC6CTL.bit.ACQPS = 8;
AdcRegs.ADCSOC9CTL.bit.ACQPS = 8;
AdcRegs.ADCSOC8CTL.bit.ACQPS = 8;
AdcRegs.ADCSOC10CTL.bit.ACQPS = 8;
AdcRegs.ADCSOC12CTL.bit.ACQPS = 8;
AdcRegs.ADCSOC14CTL.bit.ACQPS = 8;
AdcRegs.INTSEL1N2.bit.INT1SEL = 12; // ADCCH12 (ADC-B4) EOC causes ADCInterrupt 1
AdcRegs.INTSEL1N2.bit.INT1CONT = 1; // set ADCInterrupt 1 to auto clr
AdcRegs.INTSEL1N2.bit.INT1E = 1; // enable ADC interrupt 1
//Note that SOC3, 7, 11, 13 & 15 are valid, but these SOCs are not configured
//since these ADC outputs do not exist on the controlSTICK. The configuration
//is configured as it is for readability.
//EOC = end of conversion event; SOC = start of conversion event
AdcRegs.ADCINTSOCSEL1.bit.SOC0 = 1; // ADCInterrupt 1 causes SOC0
AdcRegs.ADCINTSOCSEL1.bit.SOC1 = 1;
AdcRegs.ADCINTSOCSEL1.bit.SOC2 = 1;
AdcRegs.ADCINTSOCSEL1.bit.SOC4 = 1;
AdcRegs.ADCINTSOCSEL1.bit.SOC5 = 1;
AdcRegs.ADCINTSOCSEL1.bit.SOC6 = 1;
AdcRegs.ADCINTSOCSEL2.bit.SOC8 = 1;
AdcRegs.ADCINTSOCSEL2.bit.SOC9 = 1;
AdcRegs.ADCINTSOCSEL2.bit.SOC10 = 1;
AdcRegs.ADCINTSOCSEL2.bit.SOC12 = 1;
AdcRegs.ADCINTSOCSEL2.bit.SOC14 = 1;
//Select the channel to be converted when SOCx is received
AdcRegs.ADCSOC0CTL.bit.CHSEL= 0; // convert ADC-A0 (CH0) when SOC0 is received
AdcRegs.ADCSOC1CTL.bit.CHSEL= 1; // convert ADC-A1 (CH1) when SOC1 is received
AdcRegs.ADCSOC2CTL.bit.CHSEL= 2;
AdcRegs.ADCSOC4CTL.bit.CHSEL= 4;
AdcRegs.ADCSOC5CTL.bit.CHSEL= 5;
AdcRegs.ADCSOC6CTL.bit.CHSEL= 6;
AdcRegs.ADCSOC8CTL.bit.CHSEL= 8;
AdcRegs.ADCSOC9CTL.bit.CHSEL= 9; // convert ADC-B1 (CH9) when SOC9 is received
AdcRegs.ADCSOC10CTL.bit.CHSEL= 10;
AdcRegs.ADCSOC12CTL.bit.CHSEL= 12;
AdcRegs.ADCSOC14CTL.bit.CHSEL= 14;
EDIS;
AdcRegs.ADCSOCFRC1.all = 0x1000; // kick start ADC by causing a SOC12 event
InitEPwm1Example();
InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.TINT0 = &cpu_timer0_isr;
PieVectTable.TINT1 = &cpu_timer1_isr;
PieVectTable.TINT2 = &cpu_timer2_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
// Step 4. Initialize the Device Peripheral. This function can be
// found in F2806x_CpuTimers.c
InitCpuTimers(); // For this example, only initialize the Cpu Timers
// Configure CPU-Timer 0, 1, and 2 to interrupt every second:
// 80MHz CPU Freq, 1 second Period (in uSeconds)
ConfigCpuTimer(&CpuTimer0, 80, 60);
ConfigCpuTimer(&CpuTimer1, 80, 1000000);
ConfigCpuTimer(&CpuTimer2, 80, 1000000);
// To ensure precise timing, use write-only instructions to write to the entire register. Therefore, if any
// of the configuration bits are changed in ConfigCpuTimer and InitCpuTimers (in F2806x_CpuTimers.h), the
// below settings must also be updated.
CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
CpuTimer1Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
CpuTimer2Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
// Step 5. User specific code, enable interrupts:
// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13
// which is connected to CPU-Timer 1, and CPU int 14, which is connected
// to CPU-Timer 2:
IER |= M_INT1;
IER |= M_INT13;
IER |= M_INT14;
// Enable TINT0 in the PIE: Group 1 interrupt 7
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
// Set the output relays on
GpioDataRegs.GPADAT.bit.GPIO19=1; //pin 25 relay1 to turn on
GpioDataRegs.GPADAT.bit.GPIO16=1; //pin 24 relay2 to turn on
// Step 6. IDLE loop. Just sit and loop forever (optional):
for(;;);
}
interrupt void cpu_timer0_isr(void)
{
CpuTimer0.InterruptCount++;
{
GpioDataRegs.GPADAT.bit.GPIO18 = 1; // for control loop timing
if(t>(100))
t=0.0;
t=t+60e-6;
vag=AdcResult.ADCRESULT0;//sensing the single phase sinusoidal input voltage
{
} //The sensed voltage vag has to be phase shifted by delta= 30 which is equalent to 1.6ms
EPwm1Regs.CMPA.half.CMPA = (1000*vag)+3000;//Shifted voltage has to be compared with triangle to generate pulses
GpioDataRegs.GPADAT.bit.GPIO18 = 0;
}
// Acknowledge this interrupt to receive more interrupts from group 1
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
interrupt void cpu_timer1_isr(void)
{
CpuTimer1.InterruptCount++;
// The CPU acknowledges the interrupt.
}
interrupt void cpu_timer2_isr(void)
{ EALLOW;
CpuTimer2.InterruptCount++;
{
GpioDataRegs.GPBTOGGLE.bit.GPIO34 = 1; // Toggle GPIO34 once per cycle
a=100;
}
EDIS;
// The CPU acknowledges the interrupt.
}
void InitEPwm1Example()
{
// Setup TBCLK
EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Set Compare values
EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA; // Set compare A value
EPwm1Regs.CMPB = EPWM1_MAX_CMPB; // Set Compare B value
// Setup counter mode
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count
EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM1B on event B, up count
EPwm1Regs.AQCTLB.bit.CBD = AQ_SET; // Clear PWM1B on event B, down count
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBFED = 170; // FED = 50 TBCLKs initially
EPwm1Regs.DBRED = 170; // RED = 50 TBCLKs initially
}
void InitEPwm2Example()
{
// Setup TBCLK
EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period 801 TBCLKs
EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = EPWM2_MIN_CMPA; // Set compare A value
EPwm2Regs.CMPB = EPWM2_MIN_CMPB; // Set Compare B value
// Setup counter mode
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Setup shadowing
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM1B on event B, up count
EPwm2Regs.AQCTLB.bit.CBD = AQ_SET; // Clear PWM1B on event B, down count
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm2Regs.DBFED = 170; // FED = 50 TBCLKs initially
EPwm2Regs.DBRED = 170; // RED = 50 TBCLKs initially
EPwm2Regs.AQCTLB.bit.ZRO = 0; // Clear PWM2B on zero
EPwm2Regs.AQCTLB.bit.PRD = 1 ; // Set PWM2B on period
}
void InitEPwm3Example(void)
{
// Setup TBCLK
EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD; // Set timer period 801 TBCLKs
EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
// Set Compare values
EPwm3Regs.CMPA.half.CMPA = EPWM3_MIN_CMPA; // Set compare A value
EPwm3Regs.CMPB = EPWM3_MIN_CMPB; // Set Compare B value
// Setup counter mode
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Setup shadowing
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set actions
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count
EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM1B on event B, up count
EPwm3Regs.AQCTLB.bit.CBD = AQ_SET; // Clear PWM1B on event B, down count
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm3Regs.DBFED = 170; // FED = 50 TBCLKs initially
EPwm3Regs.DBRED = 170; // RED = 50 TBCLKs initially
EPwm3Regs.AQCTLB.bit.ZRO = 0; // Clear PWM3B on zero
EPwm3Regs.AQCTLB.bit.PRD = 1 ; // Set PWM3B on period
}

Divya, here are the project files:

2476.TMS320F28027_pll.rar

Regards,

Gautam

Gautam

I got the files but which file contain the code for PLL and phase delay as per the project.

Regards

divya

I got the files but which file contain the code for PLL and phase delay as per the project.

main_2.c and adc_isr(void) seems like the function doing the operations.
(I've personally not used this project.)

Regards,

Gautam