• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 82 subscribers
  • Views 420 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

HRCAP interrupt jitter

Aron Koscho
Intellectual 580 points

I have noticed a +/-7 cycle jitter while entering the HRCAP2_Isr. The capture result is perfectly accurate, but for my application, the phase relationship between the ISR and the original sampled pulse is critical. Is there a way to reduce this jitter?

Thanks,

Aron

  • 0
    TI__Guru 60865 points

    Hi Aron,

    Any chance you are using RPT ||  assembly instructions (most likely RPT || NOP)?  These can't be interrupted, so they could lead to the ISR entry being delayed.

         

  • 0 in reply to Devin Cottier
    Intellectual 580 points

    Thanks for the reply. I was not intentionally using that instruction, and I dug through the disassembly to see if it appears in my main loop, and it does not. Any other ideas?

    Thanks,

    Aron

  • 0 in reply to Aron Koscho
    TI__Guru 60865 points

    Looking at the datasheet, it seems that this module can be clocked either synchronously or asynchronously from the SYSCLK.  

     

    Also see this forum post: http://e2e.ti.com/support/microcontrollers/c2000/f/171/p/232141/832351.aspx#832351. It looks like the allowable clock range for this module is 98MHz to 120MHz.  I think because of this you would get jitter when signals from the HRCAP module cross the synchronization boundary back into the SYSCLK domain. Possibly you could clock the HRCAP at 120MHz, and the SYSCLK at 60MHz to avoid any jitter?    

  • 0 in reply to Devin Cottier
    Intellectual 580 points

    Currently both HRCAP and SYSCLK are running at 90MHz since I require the HRCAP output to be in cycles I can load into the EPWM timer. This does have been permanence than running the HRCAP lock at 120MHz, but the jitter is still there.

  • 0 in reply to Aron Koscho
    TI__Guru 60865 points

    The following wiki page lists sources that change the ISR latency.  Some of them, like multiple-cycle instructions, seem like they will be unavoidable, but you can go through the list and see if any of them can be eliminated:

    http://processors.wiki.ti.com/index.php/Interrupt_FAQ_for_C2000

    I believe that the CLA task triggering is deterministic and the CLA has access to the ePWM registers.  Unfortunately, I don't think it can access the HRCAP, only the eCAP.

     

  • 0 in reply to Devin Cottier
    Intellectual 580 points

    Thanks for the link. It appears this jitter comes from waiting on the loops and other Multiple cycle instructions in my main code.