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F28377D Flashing ControlSuite program blinky_dc_cpu2 to CPU2

Other Parts Discussed in Thread: CONTROLSUITE, CCSTUDIO

I have just installed the latest version of CCS 6.0.0.00175, and ControlSuite 3.2.5.

I am working with the F28377D control card and trying to flash the blinky_dc examples.  I switched the active configurations to CPU1_FLASH_STANDALONE and CPU2_FLASH.  I am able to flash CPU1 with its program but I receive an error when I try to flash CPU2.  Here is the error I receive

C28xx_CPU2: Error writing the PLL values (Flash algorithm timed out). Operation cancelled.

C28xx_CPU2: Flash operation timed out waiting for the algorithm to complete. Operation cancelled.

C28xx_CPU2: Flash operation timed out waiting for the algorithm to complete. Operation cancelled.

C28xx_CPU2: GEL: File: C:\CCStudio_v6.0\controlSUITE\device_support\F2837xD\v110\F2837xD_examples_Dual\blinky_dc\cpu02\ccs\CPU2_FLASH\blinky_dc_cpu02.out: Load failed.

Any advice on what to do.

I know the hardware is fine because I have CCS 5.5 working and it can flash both CPU1 and CPU2.

Dan

  • Hi Dan,

    I am able to flash CPU1 with its program but I receive an error when I try to flash CPU2.  Here is the error I receive

    Ohh!  I need to check then... F28377D is working fine with CCSv5.5 and I've yet not tested it with CCSv6. Will test and share the results.

    Regards,

    Gautam

  • Hi Dan,

    Could you try updating to CCSV6.0.0.00190?

    Thanks and regards,
    Vamsi

  • Thank You.  Yes using CCSV6.0.0.00190 solved my problem.

     

    Dan

     

     

  • I have a similar problem, but I'm using ccs 6.0.1.00040

    Console output

  • Hi Mauro,

    CPU1 has to be connected so that Flash Plugin/debugger can access the CPU1 register space to assign the ownership of shared-RAM to CPU2 for executing the Flash Plugin code.

    Try connecting to CPU1 before doing CPU2 Flash operations using CCS Flash Plugin.

    Thanks and regards,
    Vamsi

  • ok, I verify, thank you so much
  • Hi Vamsi,

    I had the same problem. How do I connect to CPU1 and flash CPU2? Could you share the steps?

  • Wee Khee,

    Make sure to check for CCS updates and install any updates that are available from Debug Server Flash. Prefer CCSV6.0.1.

    1) Launch the target configuration from the Target configurations window (View -> Target Configurations -> Right click on the F28377D ccxml -> Launch selected configuration)

    2) Connect to CPU1 and then to CPU2 (In the debug window, select the C28xx_CPU1, right click -> Connect Target. Do the same thing for C28xx_CPU2).

    3) Reset CPU1 and then CPU2 (Select C28xx_CPU1, then in the debug window menu -> Run -> Reset -> CPU reset. Do this for C28xx_CPU2)

    4) Load the code in CPU2 (Select C28xx_CPU2 and then in the debug window menu click on "Run" -> Load -> Load program and choose the .out file that you want to load in to CPU2)

    Thanks and regards,
    Vamsi
  • Hi,

    I'm trying to run this same examples code too, using the model TMX320F28377DZWTT and CCS 6.1.2, but I cant seem to get Flash programming working. I can only get it working on RAM. I'm using this development kit TMDXDOCK28377D to program the chip.

    Correct me if I'm wrong, but all I have to do is change the active configurations to CPU1_FLASH_STANDALONE & CPU2_FLASH and click RUN>DEBUG right? After doing that, nothing happens.

    Could someone tell me what I'm doing wrong. I tried following the steps in the previous comment by Vamsi, and this is what appears in the console:

    C28xx_CPU1: GEL Output:
    Memory Map Initialization Complete
    C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. Also, CPU1 will be halted to determine SR ownership for the CPU which will run the Flash Plugin code, after which CPU1 will be set to run its application. User code execution from SR could commence after both flash banks are programmed.
    C28xx_CPU2: GEL Output:
    Memory Map Initialization Complete
    C28xx_CPU2: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. Also, CPU1 will be halted to determine SR ownership for the CPU which will run the Flash Plugin code, after which CPU1 will be set to run its application. User code execution from SR could commence after both flash banks are programmed.

  • Hi Aaron,

    Correct me if I'm wrong, but all I have to do is change the active configurations to CPU1_FLASH_STANDALONE & CPU2_FLASH and click RUN>DEBUG right? After doing that, nothing happens.

    You have issues with Flash programming or booting from flash? I don't see any error message which indicate the flash programming error hence I think issue could be with booting from flash. If you have got some error message while programming the flash then please share those messages. It'll be good if you also share the screen shot of CCS after you click on RUN -> Debug.

    Regards,

    Vivek Singh

    Note - It's always recommended to start a new E2E post for new issue.

  • Hi Vivek,

    Noted on the E2E post. I thought this was a similar topic, so I'd just continue on from here. 

    Anyway, I think I may be having issues with booting from flash. Though I'm unsure. After clicking run -> debug, if I press the 'Resume' button, then only the LED will start blinking. Yet if I turn it off and back on, it doesnt work anymore. So I'm thinking its still not doing flash programming but actually RAM.

    Here is the screen shot.

  • Look like you have booting issue. Please check the setting of BOOT-MODE pins (GPIO72/GPIO84) on the board. These should be set to 1/1 for BOOT to flash option.

    Regards,

    Vivek Singh
  • Hi Vivek,

    That works! Didnt expect it to be such a simple solution. Thank you very much!

    Best regards,
    Aaron
  • Hi Vivek

    It programs with 1/0 (GPIO71/GPIO84) but not with 1/1. what is the reason? 

  • Hi Saurabh,

    1/0 is WAITBoot and this should be used in two cases -

    • Fresh part programming - On fresh parts flash is erased and if device boots with 1/1 settings then it'll fetch 0xFFFF_FFFF which is ITRAP and it'll put the device in RESET loop and in that case when device is connected to CCS, device may be in middle of initialization and not fully initialized. To prevent this we recommend using WAITBoot.
    • Part enabled with security - If security is enable and code is running from Flash which secure then while trying to connect, ECSL triggers and disconnects the CCS so user will not be able to connect to CCS. To avoid that user should use WAITBoot mode to connect to CCS.

    Hope this helps.

    Regards,

    Vivek Singh