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Error connecting to the target: (Error 1135 @ 0x0)

Carlos Miguel Espinar
Prodigy 130 points
Other Parts Discussed in Thread: TMS320F2808, ISO7220A, ISO7220C

Hi,

I have developed a JTAG board to implement the XDS100v2, which it has the function to translate the USB protocol to JTAG protocol. I have used the same schematic of the Concerto F28M35xx controlCARD, figured in the next page:”USB to JTAG, digital iso, serial debug”. Then I have started programming the control card of Concerto F28M35xx. I have created an empty program in Code Composer v5 and I have configured the JTAG Emulator used. In this case in the option Connection I select: “Texas Instruments XDS100v2 USB Emulator” and in the option Board or Device I have select: “F28M35H52C1”. First of all, I have done the test connection and it doesn’t fail. Afterwards, I build the empty project and download it to the concerto and the programs runs correctly.

However, I do the same with the personal JTAG board connected to a control board with a TMS320F2808 DSP. Then I change the target configuration: in the option Connection I select: “Texas Instruments XDS100v2 USB Emulator” but in the option Board or Device I have select: “TMS320F2808”. First, I do the test connection and the result are positive. Afterwards, I try to build the empty project but I receive the next error message:

Error connecting to the target:

(Errorr -1135 @ 0x0) The emulator reported an error. Confirm emulator configuration and connections, reset the emulator, and retry the operation.

(Emulation package 5.1.450.0)).

 

Then I can’t download the C project to the DSP. But how it is possible if I can realize the test connection satisfactorily and I can’t download the program to the DSP? I understand when the test connection is run the information flows from the PC to the DSP and vice versa. Which could be the source error?

Thanks for your help.

  • 0
    Guru 192875 points

    Hi Carlos,

    Then I can’t download the C project to the DSP. But how it is possible if I can realize the test connection satisfactorily and I can’t download the program to the DSP? I understand when the test connection is run the information flows from the PC to the DSP and vice versa. Which could be the source error?

    There can be number of issues why this would be occuring. Please check your board and the voltage levels, does the board work with TI XDS100v2?

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    Prodigy 130 points

    Hi Gautam,

    Thanks for your reply.

    I have not a TI XDS100 v2 JTAG emulator, then I can’t test it. But I can connect my control board with a TI XDS100 v1 JTAG without any problems. Also, I can connect my control board with another JTAG emulator, then I think that apparently the problems aren’t in the control board. I have done some test connection with different control boards and JTAG emulators, having more information. I resume the test which have be done:

                    1.- Concerto F28M35xx TI controlCARD (test connection is correct)

    2.- My control board which works with F2808, connecting with XDS100 v2 (test connection is correct)

    3.- Another personal control board with F28069, connecting with XDS100 v2 (test connection failed)

    4.- My control board which works with F2808, connecting with XDS100 v1 (test connection is correct)

    I have some questions about this different tests:

    1.- The differences between all the test are in the two next steps:

                    The test for the JTAG DR bypass path-length

    The test for the JTAG IR instruction path-length

    Why change the results in each test?

    2.- How it is possible that the test connection with my JTAG XDS100v2 runs correctly with a control board with F2808 and it fails when the test connection was done with a control board with F28069? Both are used with JTAG XDS100 v1 and the test connections runs correctly and I can debug without any problems.

    3.- When the Code Composer executes the test connection, are there messages transfer between the PC and the DSP? If yes, why the PC cannot download the C program to the DSP with the XDS100 v2 with my control board? (I have the same problem with the control board which runs with F28069)

    I hope the description of the test done and the files attached will be used to solve the problems.

    I can do another test? I wanted to see the messages sent to the DSP when the C program is download to the DSP, comparing the messages sent by the Concerto F28M35xx TI controlCARD and my control board running with the XDS100 v2. But this test is so difficult because the date frame is so long.

    Thanks for your help.

    Fullscreen 3568.Concerto F28M35xx TI controlCARD .txt Download 
    [Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\CARLOS~1\AppData\Local\.TI\693494126\
    0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Mar  9 2014'.
The library build time was '22:27:48'.
The library package version is '5.1.450.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 512 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End]

    Fullscreen 0334.test_f2808_XDS100_v1.txt Download 
    [Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\CARLOS~1\AppData\Local\.TI\693494126\
    0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Mar  9 2014'.
The library build time was '22:27:48'.
The library package version is '5.1.450.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 512 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 38 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End]

    Fullscreen 1031.test_f2808_XDS100_v2.txt Download 
    [Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\CARLOS~1\AppData\Local\.TI\693494126\
    0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Mar  9 2014'.
The library build time was '22:27:48'.
The library package version is '5.1.450.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 512 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 39 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 2 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End]

    Fullscreen 0143.test_f28069_XDS100_v2.txt Download 
    [Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\PUESTA~1\AppData\Local\.TI\693494126\
    0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Aug 20 2013'.
The library build time was '22:56:19'.
The library package version is '5.1.232.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 512 32-bit words.

The test for the JTAG IR instruction path-length failed.
The many-ones then many-zeros tested length was 39 bits.
The many-zeros then many-ones tested length was -16352 bits.

The test for the JTAG DR bypass path-length failed.
The many-ones then many-zeros tested length was 2 bits.
The many-zeros then many-ones tested length was -16352 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Test 1 Word 0: scanned out 0xFFFFFFFF and scanned in 0x06BE7B13.
Test 1 Word 1: scanned out 0xFFFFFFFF and scanned in 0xFFFFFF88.
Scan tests: 1, skipped: 0, failed: 1
Do a test using 0x00000000.
Test 2 Word 0: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 1: scanned out 0x00000000 and scanned in 0x0000007F.
Scan tests: 2, skipped: 0, failed: 2
Do a test using 0xFE03E0E2.
Test 3 Word 0: scanned out 0xFE03E0E2 and scanned in 0x00000001.
Test 3 Word 1: scanned out 0xFE03E0E2 and scanned in 0x01F07100.
Test 3 Word 2: scanned out 0xFE03E0E2 and scanned in 0x01F0717F.
Test 3 Word 3: scanned out 0xFE03E0E2 and scanned in 0x01F0717F.
The details of the first 8 errors have been provided.
The utility will now report only the count of failed tests.
Scan tests: 3, skipped: 0, failed: 3
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 4
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 5
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 6
Some of the values were corrupted - 66.8 percent.

The JTAG IR Integrity scan-test has failed.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Test 1 Word 0: scanned out 0xFFFFFFFF and scanned in 0xFFFFFFFD.
Scan tests: 1, skipped: 0, failed: 1
Do a test using 0x00000000.
Test 2 Word 0: scanned out 0x00000000 and scanned in 0x00000003.
Scan tests: 2, skipped: 0, failed: 2
Do a test using 0xFE03E0E2.
Test 3 Word 0: scanned out 0xFE03E0E2 and scanned in 0xF80F8389.
Test 3 Word 1: scanned out 0xFE03E0E2 and scanned in 0xF80F838B.
Test 3 Word 2: scanned out 0xFE03E0E2 and scanned in 0xF80F838B.
Test 3 Word 3: scanned out 0xFE03E0E2 and scanned in 0xF80F838B.
Test 3 Word 4: scanned out 0xFE03E0E2 and scanned in 0xF80F838B.
Test 3 Word 5: scanned out 0xFE03E0E2 and scanned in 0xF80F838B.
The details of the first 8 errors have been provided.
The utility will now report only the count of failed tests.
Scan tests: 3, skipped: 0, failed: 3
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 4
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 5
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 6
Some of the values were corrupted - 66.7 percent.

The JTAG DR Integrity scan-test has failed.

[End]

  • 0 in reply to Carlos Miguel Espinar
    Prodigy 130 points

    Hi everybody,

    I want to explain which my error in the PCB configuration was. In the first case, I read the schematic Concert kit board from the revision 1.0 and the problem was in the digital isolator ISO7220AC. I put in my PCB this one and the debug with the DSP failed. Then I read in other post and in the new version of the schematic that the correct digital isolator should be ISO7220CD. This other one digital isolator has a higher propagation speed and lower delay time.

    Then, I have only changed this component and I can debug the program in all platforms with different DSPs.

    Regards. 

  • 0 in reply to Carlos Miguel Espinar
    Guru 192875 points

    That's Great, Carlos!

    Goodluck & Regards,

    Gautam

  • 0 in reply to Carlos Miguel Espinar
    Guru 13185 points

    Carlos Miguel Espinar said:
    the problem was in the digital isolator ISO7220AC

    Hello Carlos,

    My board also uses ISO7220A, and I got this solution from the forum

    http://e2e.ti.com/support/microcontrollers/c2000/f/171/p/321906/1120577.aspx#1120577

    You may try it and see whether it works for you.

    But indeed, using ISO7220C (or M) is better and recommended.

    Best regards,

    Maria