28069 ADC Clock

Hello,

I am using a TI HV RESONANT LLC KIT with a 28069 control card.

I am trying to understand what the ADCCLK is being set to.

I noticed after stepping through the kit's initialization code that ADCCTL2 = 0x0000

The TMS320x2806x Piccolo Technical Reference Manual states the following in regard to register ADCCTL2:

When enabled, divides the ADC input clock by 2. When running /2 ADCCLK, scale the minimum sample duration accordingly to meet 116.6ns for better throughput.

     0 ADC clock = CPU clock
     1 ADC clock = CPU clock/2

Combined with the CLKDIV4EN bit, this determines the ADC Clock to CPU Clock ratio.

CLKDIV2EN      CLKDIV4EN      ADCCLK

        0                         0                SYSCLK
        0                         1                SYSCLK
        1                         0                SYSCLK / 2
        1                         1                SYSCLK / 4

The 28069 control card is operating at 80MHZ => SYSCLK. 

This seems to imply that the ADCCLK is running at 80MHZ?

But if you look at the 28069 data sheet Table 5-1 it states the MAX ADCCLK is 0.5 of the SYSCLK which in my case would be 40MHZ.

Even though the kit’s software is NOT setting the CLKDIV2EN bit in the ADCCTL2 register, is the ADCCLK running at 40MHZ?

Thanks,

Brent