Hi guys, I'm following signal processing project that use TI Concerto ADC to sample signal data and then process it. My question is that: Would the MCU be more and more unstable if I spend too much time in an ADC interrupt before returning to the main while loop? It seems that I get quite a lot of illegal ISR when I increase the amount of computation inside an ADC interrupt routine. However, if I reduce the burden of the ISR, the algorithm becomes more stable. I wonder if there is a clock cycle limit for an ADC interrupt.