change ramfuncs section from L0 SARAM to M0+M1 SARAM

l.hauchecorne

Hello,

I'm programming a F28027F and I'd like to get more ram for global vars, thus I'm playing with the .cmd but I've some questions and problems.

On the original code, the ram funcs are located in L0 :

   RAMM0_M1    : origin = 0x000000, length = 0x000800     /* on-chip RAM block M0 + M1 */
   DRAML0      : origin = 0x008800, length = 0x000800     /* on-chip RAM block L0 */
   FLASHB      : origin = 0x3F4000, length = 0x002000     /* on-chip FLASH */

   .cinit              : > FLASHC_D     PAGE = 0
   .pinit              : > FLASHC_D,    PAGE = 0
   .text               : > FLASHC_D     PAGE = 0
   codestart           : > BEGIN        PAGE = 0
   ramfuncs            : LOAD = FLASHB,
                         RUN = DRAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         PAGE = 1

   csmpasswds          : > CSM_PWL_P0   PAGE = 0
   csm_rsvd            : > CSM_RSVD     PAGE = 0
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0_M1   PAGE = 1
   .ebss               : > RAMM0_M1   PAGE = 1
   .esysmem            : > RAMM0_M1   PAGE = 1

As you can see, 0x8000 to 0x8800 are not used...

I though about 2 ways to use them, the first : make .ebss to be placed in RAMM0_M1 and say DRAML1 (from 8000h to 8800h). But the only things I've found about that is to place the section on RAMM0 XOR DRAML1, but not both.

The Second way was to move the ram functions to RAMM0_M1... but there the code doesn't work, falling in a PIE_illegalIsr

(among the ram func, there are ISR, actually, The code is based on the Motor Ware)

Thus, yet, is this possible ?

then, why shall the code bug moving the ram funcs ? (btw, if _RamfuncsRunStart were not set by the linker, it would be logical, but the symbol point to 0x0...)

Also, why this restriction about not to expand a section on another address range ?

Thank you for reading :)

Léo.

over 11 years ago

0 l.hauchecorne over 11 years ago

Prodigy 20 points

Hey again;

I think I've found a solution :

I create a custom data section, say named "buffers" that points to DRAML0 (I renamed it to match the order of the memory areas), then I use a pragma DATA_SECTION to make my buffers to go in this section. That works.

...This is how looks my .cmd file now :

MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

   /*RAMUSER     : origin = 0x000100, length = 0x000300     /* on-chip USER RAM block */
   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
   FLASHC_D    : origin = 0x3F0000, length = 0x004000     /* on-chip FLASH C and D */
   FLASHA      : origin = 0x3F6000, length = 0x001F80     /* on-chip FLASH A */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   IQTABLES    : origin = 0x3FE000, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEB50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FEBDC, length = 0x0000AA	  /* IQ Math Tables in Boot ROM */

   ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

/*   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
/*   RAMM0       : origin = 0x000000, length = 0x000100     /* on-chip RAM block M0 */
/*   RAMM0_M1    : origin = 0x000050, length = 0x0005B0     /* on-chip RAM block M0 + M1 */
   RAMM0_M1    : origin = 0x000000, length = 0x000800     /* on-chip RAM block M0 + M1 */
   DRAML0_0      : origin = 0x008000, length = 0x000800     /* on-chip RAM block L0 - 0 */
   DRAML0_1      : origin = 0x008800, length = 0x000800     /* on-chip RAM block L0 - 1 */
   FLASHB      : origin = 0x3F4000, length = 0x002000     /* on-chip FLASH */
}

SECTIONS
{
   //userfuncs           : > RAMUSER     PAGE = 0

   /* Allocate program areas: */
   .cinit              : > FLASHC_D     PAGE = 0
   .pinit              : > FLASHC_D,    PAGE = 0
   .text               : > FLASHC_D     PAGE = 0
   codestart           : > BEGIN        PAGE = 0
   ramfuncs            : LOAD = FLASHB,
                         RUN = DRAML0_1,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         PAGE = 1

   csmpasswds          : > CSM_PWL_P0   PAGE = 0
   csm_rsvd            : > CSM_RSVD     PAGE = 0

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0_M1   PAGE = 1
   .ebss               : > RAMM0_M1   PAGE = 1
   .esysmem            : > RAMM0_M1   PAGE = 1
   buffers             : > DRAML0_0   PAGE = 1 /**/

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHC_D     PAGE = 0
   .switch             : > FLASHC_D     PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : > FLASHC_D     PAGE = 0            /* Math Code */
   IQmathTables        : > IQTABLES,    PAGE = 0, TYPE = NOLOAD


   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT

}

But the question about the ram ISRs is still not answered (why doesn't it work when ram funcs are not in L0?)

...I think it 's because L0 is dual mapped, but this architecture is for compatibility purpose as it's said in the docs...

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change ramfuncs section from L0 SARAM to M0+M1 SARAM