TI HV RESONANT LLC KIT - ADC samples

Brent,

This is to get around the ADC first sample issue that exist in some of our C2000 MCUs, such as the F28027.  Note that here we are sampling the ADC channels at four separate times (4 SOC trigger points). 
(post modification: made the above more clear)

Take a look at the "ADC: Initial Conversion" advisory in the Errata.  Sampling an ADC twice (doing a dummy sample) is one method of avoiding the issue.  The other, on RevA and later silicon, is to use the ADCNONOVERLAP and CLK2DIVEN bits of the ADC.  The choice between which of these two is better depends on your use-case.

Hopefully this helps!


Thank you,
Brett

This is for the errata related to adc initial conversion , refer:

http://www.ti.com/lit/er/sprz295k/sprz295k.pdf

Thanks for the reply Brett.

I had a couple questions for clarification.

1)  In the kit's code I pasted above aren't there actually 10 SOC (0 - 9)?  I may need to reread what a SOC is.

2) I had read the 2803x errata talking about this.  From reading the errata:

          For sequential mode, discard the first sample at the beginning of every series of

          conversions. For instance, if the application calls for a given series of conversions,

          SOC0→SOC1→SOC2, to initiate periodically, then set up the series instead as

          SOC0→SOC1→SOC2→SOC3 and only use the last three conversions, ADCRESULT1,

          ADCRESULT2, ADCRESULT3, thereby discarding ADCRESULT0.

This would seem to indicate just SOC0 would need to be “dumped”.  If that is the case, I am not sure why in the kit’s code they are sampling each input twice (i.e. have 2 separate SOC for each ADC input)?

If it is only SOC0 that needs to be dumped, in essence the number of usable ADC channels is 15?

If you need to assign 2 SOC per ADC channel, in essence the number of usable ADC channels is 8?

3) Does this hold for the 2806x (this is the controlCard I am using with the HVLLC kit)?  I cannot find the errata for it => SPRZ342.  If I click on the link for this document at the bottom of the 28069 data sheet it says it cannot find the document.  The same goes for a link I found in a community post http://www.ti.com/lit/pdf/sprz342.  Or http://www.ti.com/product/tms320f28069.

4) The other work around for REV A silicon (2803x), you are running at ½ the CPU clock speed.  The 28069 is on REV D.  I am running at 80MHZ, is there a base ADC Clock I could run at to avoid this issue?

Thanks for your help,

Brent

Sorry meant 8 SOC in question 1) not 10

I'll check up on why the F2806x Errata is missing in action.

-Brett

Thanks for the reply Brett.

That makes sense.  So in essence for any sample, you need to sample twice unless you are running at the slower ADC clock rate.

In our application we need 15 ADC inputs.

2 of ADC channels would trigger off of 2 different PWM signals.

For the other 13 ADC inputs I was planning on using 1 SOC trigger – cpu timer - to read the 13 result registers of the other 13 ADC inputs.

With the 2 ADC channels triggering off the 2 different PWM signals, that eats 4 of the SOC channel selects leaving only 12.  I would need to have 14 for the other ADC channels tied to the cpu timer SOC trigger (13 for the other ADC channels + 1 for the dummy read).

It may not be a problem on the 28069 because the 28069 has a max ADC clock rate of 45MHZ when running at 90MHZ (i.e. so you need to set AdcRegs.ADCCTL2.bit.CLKDIV2EN = 1 anyway).   I am running at 80MHZ and 40MHZ ADC Clock.  So I believe it is just a matter of setting the ADCNONOVERLAP bit (if that is what the 28069 errata states?) and I should be ok to NOT have to sample twice (i.e. could do the following)??

            ChSel[0] = 9;               // B1 - Ipri

            ChSel[1] = 7;               // A7 – Vout

            ChSel[2] = 0;               // A0

            ChSel[3] = 1;               // A1

            ChSel[4] = 2;               // A2

            ChSel[5] = 3;               // A3

            ChSel[6] = 4;               // A4

            ChSel[7] = 5;               // A5

            ChSel[8] = 6;               // A6

            ChSel[9] = 8;               // B0

            ChSel[10] = 10;           // B2

            ChSel[11] = 11;           // B3

            ChSel[12] = 12;           // B4

            ChSel[13] = 13;           // B5

            ChSel[14] = 14;           // B6

            ChSel[15] = 15;           // B7

           // ADC Trigger Selection

            TrigSel[0] = ADCTRIG_EPWM1_SOCA;      // ePWM1, ADCSOCA

            TrigSel[1] = ADCTRIG_EPWM1_SOCA;      // ePWM1, ADCSOCA

            TrigSel[2] = ADCTRIG_CPU_TINT; 

            TrigSel[3] = ADCTRIG_CPU_TINT; 

            TrigSel[4] = ADCTRIG_CPU_TINT; 

            TrigSel[5] = ADCTRIG_CPU_TINT; 

            TrigSel[6] = ADCTRIG_CPU_TINT; 

            TrigSel[7] = ADCTRIG_CPU_TINT; 

            TrigSel[8] = ADCTRIG_CPU_TINT; 

            TrigSel[9] = ADCTRIG_CPU_TINT; 

            TrigSel[10] = ADCTRIG_CPU_TINT; 

            TrigSel[11] = ADCTRIG_CPU_TINT;           

            TrigSel[12] = ADCTRIG_CPU_TINT;           

            TrigSel[13] = ADCTRIG_CPU_TINT;           

            TrigSel[14] = ADCTRIG_CPU_TINT;           

            TrigSel[15] = ADCTRIG_CPU_TINT;           

Sorry again for your help and thanks for trying to find the 28069 errata. 

Brent

Hi Brent,

The 'F28069 errata is back online. 

Thanks for letting us know about the problem.


-Brett

Thanks Brett,

Just one point of clarification.  This particular issue states affected revisions are 0, A, B.

Piccolo is now on D.

I take it this mean D no longer has this issue?

Thanks,

Brent

What do you mean by "Piccolo is now on D"?

As of today's date: F2806x is currently on RevB, F28035 is currently on RevA

Thank you,
Brett

Sorry my bad, I saw the following and incorrectly assumed it meant silicon rev

Thanks again for your help,

Brent

FYI:
For C2000, the Errata guides are always the best place to figure out which revisions are in-the-wild.

-Brett