Hello,
My target is a TMS320F28335.
I have been having this strange issue where the first of eight SPI interrupts always takes 100us to call the
SPIA ISR. The next 7 interrupts take 4us to enter the body of the SPIA ISR.
I am suspecting the problem is causes by sharing of resources as shown below. The issue is with the Serial DAC.
SPIA (4.69MHz) --> Serial DAC and 8 channel ADC (=ADC#1)
McBSPA (Uses DMA, 9.38MHz) --> 8 channel ADC (=ADC#2)
MCBSPB (Uses DMA, 9.38MHz) --> 8 channel ADC (=ADC#3) and serial RAM
My application runs in the following way.
1. A timer interrupt happens (every 130us)
2. The timer ISR starts simultaneous ADC conversions for three serial 8 channel ADCs (ADC#1,ADC#2,ADC#3).
3. The ADC conversion interrupt happens.
4. The ADC conversion complete ISR sets up the SPIA (Uses FIFO), MCBSPA, MCBSPB and DMA channel 1 (MCBSPA TX), DMA Channel 2 (MCBSPA RX), DMA Channel 3 (MCBSPB TX) DMA Channel 4 (MCBSPB RX) to retrieve data from the three ADCs.
5. The SPIA and DMA interrupts happen. My application is coded so the SPI interrupt occurs last.
6. The SPIA ISR sets up the SPIA to send one 16 bit data item to the serial ADC and then enables the SPIA interrupt. Also, at this time the SPIA ISR sets up the DMA to transmit the data to the Serial RAM. (However, for testing this issue, I disabled the DMA setup for transmitting to the serial RAM.)
7. The SPIA interrupt happens.
8. step 6 repeats another 7 times. The SPIA interrupt is disabled the last time the SPIA ISR.
The problem occurs the first time the SPIA ISR is called (Step 6). It takes the uP 100us to make the first call the SPIA ISR.
I have disabled almost all the code (including saving to RAM, i.e. using the MCBSPB) except for the code that executes the process above.
If I remove steps 2-5, the 100us delay doesn't happen.
Is there any issue with the SPIA with regards to changing from FIFO to non-FIFO mode?
Stephen
