Other Parts Discussed in Thread: CONTROLSUITE
Hi,
I have a problem between the RAMPSTS register value and the 10-DAC set value. First of all I use the contoller to control a buck converter, also I configure the ramp and the comparator as fallow:
/* Configure the comparator: if A > B -> 1, else -> 0 */
SysCtrlRegs.PCLKCR3.bit.COMP2ENCLK = 1; /* Enable clock to the Comparator 2 block */
Comp2Regs.COMPCTL.bit.COMPDACEN = 1; /* Power up Comparator 1 locally */
Comp2Regs.COMPCTL.bit.COMPSOURCE = 0; /* Connect the not inverting input to the internal DAC */
Comp2Regs.COMPCTL.bit.CMPINV = 1; /* Inverted output of the comparator is passed */
Comp2Regs.DACVAL.bit.DACVAL = 0; /* Set DAC output to midpoint */
Comp2Regs.COMPCTL.bit.SYNCSEL = 0; /* Asynchronous version of the comparator
Comp2Regs.COMPCTL.bit.QUALSEL = 1; /* Input to the block must be consistent for x+1 consecutive clocks */
Comp2Regs.DACCTL.bit.RAMPSOURCE = 4; /* Ramp source is ePWM5 */
Comp2Regs.DACCTL.bit.DACSOURCE = 1; /* With ramp generator */
Comp2Regs.RAMPDECVAL_SHDW = 8;
Assume that I set the RAMPMAXREFS = 12800 and also I set the RAMPDECVALS = 8.
My issue is:
In debug mode:
- I observe that the RAMPSTS is decreasing each SYSCLK (60MHz) by the value into RAMPDECVALS, but in debug mode I can't use the power output so the comparator input voltage sense is alway at 0, so in this case the PWM is limited by software event qualifier.
- The RAMPSTS is reset at each 96kHz as set by the PWM5 who is TBCLK = 624, see PWM5 setup below:
EALLOW;
{
/* Timer setup preset, clear and phase */
EPwm5Regs.TBPRD = ( 624 ); /* Set PWM period 96kHz @ 60MHz clock */
EPwm5Regs.TBPHS.half.TBPHS = 0x0000; /* Set phase register to zero */
EPwm5Regs.TBCTR = 0x0000; /* Clear counter */
/* Setup TBCLK */
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; /* UP count which is asymmetrical mode */
EPwm5Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Phase loading desable */
EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; /* Clock ratio to SYSCLKOUT is Divide by 1 */
EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1; /* Div by 1. TBCLK = SYSCLKOUT / (HSPCLKDIV * CLKDIV) */
EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW; /* Set shadow register load */
/* Setup Counter-Compare */
EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; /* Load shadow register CMPA every ZERO */
EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; /* Load shadow register CMPB every ZERO */
EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; /* Active CMPA load from shadow mode when CTR = Zero */
EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; /* Active CMPB load from shadow mode when CTR = Zero */
/* Configure the deadband submodule */
EPwm5Regs.DBCTL.bit.IN_MODE = 0; /* PWM1A is the DB source for rising/falling edge */
EPwm5Regs.DBCTL.bit.OUT_MODE = 0; /* The rising-edge delayed signal is seen on output EPWMxA */
EPwm5Regs.DBRED = DEAD_BAND_RISING; /* Rising edge delay */
/* Enable TZ1 as trip source */
EPwm5Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;
/* Enable one shot interrupt (uncomment if useful) */
EPwm5Regs.TZEINT.bit.OST = 1;
/* Force all PWM outputs at low state when trip occurs */
EPwm5Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm5Regs.AQCTLA.bit.ZRO = AQ_SET; /* When AQCTLA = Zero set EPWMxA output high */
EPwm5Regs.CMPB = 312; /* CMPA event when it reaches this value */
EPwm5Regs.AQCTLA.bit.CBU = AQ_CLEAR; /* CMPA: Set (variable) */
}
EDIS;
- When I disengage the debug mode and I use my output power, at the input sense voltage I observe triangular wave form as expected, although then I previously observe the RAMPSTS register desreasing during an half cycle of my full bridge PWM, the comparator is still triggering at the RAMPMAXREFA = 12800 -> 10 bit MSB = 200. That is special for my point of view, but I think I missed a configuration, but I can find it.
If you need more information, I can give it to you, but I will need to have a private room with you, because I can write into this forum some sensitive information.
Regards,
Marc-Olivier Brassard, Jr. Eng.
Electronic designer
