I have a couple of questions about the PWM trip functionality.
1. There are two versions of the TZCLR register, labeled TZCLR / TZCLRM. What does the mirror version do? It is not explained anywhere in the TRM.
2. The trip zone signals TZ5 and TZ6 are briefly described as indicating clock failure or emulation stop. I can't find any more detail on when they trip. Are they good ways to guard the PWM output against processor failure and halting execution or breakpoints in the debugger? Is that what they mean?
Thanks for any help!
