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SPI On F28377D

Other Parts Discussed in Thread: CONTROLSUITE

Dear All I am posting this problem for second time as I have received any reply from TI team. 

I am facing some problem for interfacing SPI on F28377d with slave SPI IC.  

1. - I am using CCS5.5 updated and I can not see SPICCR register for any SPI module a,b,c.  I can see all other registers of SPI module in register view window. Is there any way to see that register. ---

Received way out in earlier post from Brett-----

2. - I am trying to interface a SPI slave IC. To start with, I tried Control suit example of SPI loop back with modification of 8 bit character length. In Debug mode, I see same data in SPIRXbuf after transmission,

If I transmit 8 data 0x98 i.e.0x9800 left justified 8 bit data then I expect SPI RX buf to be 0x0098, right justified received 8 bit data 

instead  I get 0x9800 in SPI RXbuf.

I removed internal loop back mode and made external shorting of MOSI & MISO pins th' a buffer again the same result

3. Similarly when I connect external SPI slave  chip and view data on CRO I get transition on MISO pin but do not get physical data in SPIRXBUF. I get same data which I transmit as explained above.

I can see proper clock during  transmission, proper data on MOSI pin . Data pattern changes as soon as I change data.

4. I have defined GPIO 16/17/18/19 as peripheral pins. and checked if particular GPIO pin corresponding to MISO function work fine when defined as I/P . So there is no problem as far as hardware is concern 

It looks like in SPI mode either MISO data is not getting connected to SPIRXBUF

Can concern TI employee resolve my problem?

thanks in advance

Abhijit

  • Please read AS

    Dear All I am posting this problem for second time as I have NOT received any reply from TI team. 

  • Abhijit,

    I can try and help you out. I am sorry that you have had to post twice in order to get a response.

    1. I have confirmed that this is true on my CCSv5 install as well. This seems to be a mistake in the tools, and I have already fed it back to the correct parties to be fixed.

    2./3. I have tried on my bench set up and am unfortunately unable to replicate your behavior.

    If I modify the spi_loopback_cpu01 project found in ControlSuite (F2837xD v110) for 8bit data I am correctly seeing the data in both SPIDAT as well as SPIRXBUF. This is the case with both internal loopback and using the same GPIOs as you. 

    Can you please provide me with a little more information so I can dig in further?

    - Are you using a custom board? TI evaluation kit?
    - Are you using FIFO, DMA?
    - What external SPI Slave are you working with?

    Also, here is the code I have messed around with, please run this and share your results. I removed FIFO to eliminate a tiny bit of complexity. you can add them back in if you want to.

    //###########################################################################
    // FILE:   Example_28X7xSpi_FFDLB.c
    // TITLE:  SPI Digital Loop Back program.
    //
    //! \addtogroup cpu01_example_list
    //! <h1>SPI Digital Loop Back</h1>
    //!
    //!  This program uses the internal loop back test mode of the peripheral.
    //!  Other then boot mode pin configuration, no other hardware configuration
    //!  is required. Interrupts are not used.
    //!
    //!  A stream of data is sent and then compared to the received stream.
    //!  The sent data looks like this: \n
    //!  0000 0001 0002 0003 0004 0005 0006 0007 .... FFFE FFFF \n
    //!  This pattern is repeated forever.
    //!
    //!  \b Watch \b Variables \n
    //!  - \b sdata , sent data
    //!  - \b rdata , received data
    //		
    //###########################################################################
    // $TI Release: F2837xD Support Library v110 $
    // $Release Date: Mon Apr  7 10:35:37 CDT 2014 $
    //###########################################################################
    
    #include "F28x_Project.h"     // Device Headerfile and Examples Include File
    
    // Prototype statements for functions found within this file.
    // __interrupt void ISRTimer2(void);
    void delay_loop(void);
    void spi_xmit(Uint16 a);
    void spi_fifo_init(void);
    void spi_init(void);
    void error(void);
    
    #define WORDLENGTH 0x7	// 8 bit chars
    
    void main(void)
    {
    	int i = 0;
       Uint16 sdata;  // send data
       Uint16 rdata;  // received data
       
    // Step 1. Initialize System Control:
    // PLL, WatchDog, enable Peripheral Clocks
    // This example function is found in the F2837xD_SysCtrl.c file.
       InitSysCtrl();
    
    // Step 2. Initialize GPIO: 
    // This example function is found in the F2837xD_Gpio.c file and
    // illustrates how to set the GPIO to it's default state.
    // InitGpio();  // Skipped for this example  
    // Setup only the GP I/O only for SPI-A functionality
    // This function is found in F2837xD_Spi.c
       InitSpiaGpio();
    
    // Step 3. Clear all __interrupts and initialize PIE vector table:
    // Disable CPU __interrupts 
       DINT;
    
    // Initialize PIE control registers to their default state.
    // The default state is all PIE __interrupts disabled and flags
    // are cleared.  
    // This function is found in the F2837xD_PieCtrl.c file.
       InitPieCtrl();
    
    // Disable CPU __interrupts and clear all CPU __interrupt flags:
       IER = 0x0000;
       IFR = 0x0000;
       
    // Initialize the PIE vector table with pointers to the shell Interrupt 
    // Service Routines (ISR).  
    // This will populate the entire table, even if the __interrupt
    // is not used in this example.  This is useful for debug purposes.
    // The shell ISR routines are found in F2837xD_DefaultIsr.c.
    // This function is found in F2837xD_PieVect.c.
       InitPieVectTable();
    	
    // Step 4. Initialize all the Device Peripherals:
    // This function is found in F2837xD_InitPeripherals.c
    // InitPeripherals(); // Not required for this example
    
    
       // comment out for non fifo (uncomment for fifo mode)
    //   spi_fifo_init();	  // Initialize the Spi FIFO
    
    
       spi_init();		  // init SPI
    
    // Step 5. User specific code:
    // Interrupts are not used in this example. 
       sdata = 0x0000;							
       while(1)
       {
    	   for(i=1;i<=0xF;i++)
    	   {
    		   // Transmit data
    		   spi_xmit(i);
    		   // Wait until data is received
    //		   while(SpiaRegs.SPIFFRX.bit.RXFFST !=1) { }		// Uncomment for FIFO
    		   while(SpiaRegs.SPISTS.bit.INT_FLAG != 1) {}		// COMMENT this line if using FIFO
    		   // Check against sent data
    		   rdata = SpiaRegs.SPIRXBUF;
    		   if(rdata != i) ESTOP0;
    		   asm("  nop");
    	   }
       }
    } 	
    
    // Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here:	
    
    void delay_loop()
    {
        long      i;
        for (i = 0; i < 1000000; i++) {}
    }
    
    void error(void)
    {
       asm("     ESTOP0");						// Test failed!! Stop!
        for (;;);
    }
    
    void spi_init()
    {    
    	SpiaRegs.SPICCR.all =0x0000|WORDLENGTH;		// Reset on, rising edge, WORDLENGTH char bits
    	SpiaRegs.SPICTL.all =0x0006;    		    // Enable master mode, normal phase,
                                                    // enable talk, and SPI int disabled.
    	SpiaRegs.SPIBRR =0x007F;									
    //    SpiaRegs.SPICCR.all =0x0090|WORDLENGTH	// Relinquish SPI from Reset (LB mode)
        SpiaRegs.SPICCR.all =0x0080|WORDLENGTH;		// Relinquish SPI from Reset (external loopback mode)
        SpiaRegs.SPIPRI.bit.FREE = 1;               // Set so breakpoints don't disturb xmission
    }
    
    void spi_xmit(Uint16 a)
    {
    	Uint16 data;
    	data = a<<8;		// left shift tx data 8 bits.
        SpiaRegs.SPITXBUF = data;
    }    
    
    void spi_fifo_init()										
    {
    // Initialize SPI FIFO registers
        SpiaRegs.SPIFFTX.all=0xE040;
        SpiaRegs.SPIFFRX.all=0x2044;
        SpiaRegs.SPIFFCT.all=0x0;
    }  
    
    //===========================================================================
    // No more.
    //===========================================================================
    
    

    -Mark

  • Mark,

    thanks for replying.

    Strange!!!

    IS my assumption of 8 bit data values of 0x9800 for sending and 0x0098 for receiving is correct?

    to answer your queries 

    - I am using TI evaluation F2837x control Card(R1.1)  with control card docking station (R4.1)

    - I have enabled FIFO as it is already there in Control Suit example but not DMA. I will require to  use FIFO as well as DMA in future so may have to make configuration accordingly.

    - It is Quadrature Encoder interface IC of LSI/CSI. I have attached data sheet for your reference.0410.LS7366R.pdf 

    I have not attached my code. 

    I will check your C code and come back to U

    thanks again

    Abhijit 

  • Hi Abhijit,

    Couple of important points.

    1. Your assumption about transmitting 0x9800 and receiving 0x0098 is correct provided you are operating in 8bit mode. You mentioned that you are. But still to confirm that,  the last 4 bits in SPICCR need to be 0111b.

    2. When interfacing with SPI slave CLOCK POLARITY (Bit 6 of SPICCR) and CLOCK PHASE (Bit 3 of SPICTL) play an important role. Looking at the data sheet of your slave device, seems to me like CLOCK POLARITY needs to be at 0 and CLOCK PHASE needs to be at 1. Try if it works with these settings. (In case it does not work change the value in CLOCK PHASE to 0 and try again. But do not change the value of CLOCK POLARITY. It is clear from slave datasheet that clock needs to be low when idle.)

    Vivek

    (P.S: Just wanted to let you know C2000 processors have QEP modules inbuilt. So you can interface encoders directly to them. A special IC is not needed in between unless you have some specific reason.)

  • Hi. Vivek ,

    thanks for reply.

    1. Yes I will check SPICCR content for correct 8 bit operation

    2. OK - Have already done that

    Yes I know C2000 is having in built QEP. I am using it in my current system but in my future project I want to interface 8 such QE and there are max. 3 available in F28377 so I thought of using it.

    any way thanks.

    regards

    Abhijit

  • Mark,

    I just checked modified program you had attached earlier.

    It is working fine at my end also. It means that there is some problem with FIFO configuration given in example. As you have just marked FIFO configuration and written separate configuration and checking Int _Flag in place of RXFFST_bit.

    I get 0x0001 data after sending 0x0100 data from SPIDAT.

    Is 8 bit transmission is not available for FIFO module?

    Please let me know.

    -Abhijit