Nesting of Interrupts in a User Defined Trap ISR

stevenh

Guru 20075 points

Hello,

I want to make sure a PIE group 1 ISR gets called during a user defined trap ISR.

I have already looked through the nesting wiki and it seems that nesting interrupts in a user defined trap ISR is easier than an ISR associated with one of the PIE groups.

I am thinking of nesting group 1 interrupts in the user defined trap ISR could be coded as:

interrupt void userDefineTrapISR(void)
{
     IER = M_INT1;
     asm("            NOP");
     EINT;
     do something
     DINT;
}

Am I correct?

Also, am confused about the example code in the nesting wiki.

Isn't

IER |= M_INT2;
IER &= M_INT2;

The same as

IER = M_INT2;

Stephen

over 12 years ago

0 stevenh over 12 years ago

Guru 20075 points

Hello,

Just a little more information.

My code is generating the user defined interrupt from an ISR as shown below. I just found out throught testing that the user defined ISR is called before the someISR completes. I DIDN't allow nesting of any interrupts at the start of someISR, so why is the user defined ISR being called before someISR completes?

Stephen

interrupt void someISR(void)
{
    ...

    if (somethingHappend)
    {
       asm(" TRAP #20");
    }
   
    ...
}

0 stevenh over 12 years ago in reply to stevenh

Guru 20075 points

Ok...

According to 3.5.2 (page 97) of http://www.ti.com/lit/ug/spru430e/spru430e.pdf:

1. The IER and IFR are not affected by the TRAP ISR.

2. INTM is set when calling the ISR, so interrupts are globally disabled.

Therefore, nesting is automatic if I just clear INTM (enable interrupts globally).

Also, it seems the user defined trap interrupt is called right away. Why would it be called right away if I haven't cleared INTM in the someISR described above?

Also, spru430e.pdf doesn't say anything about INTM being cleared on return from the userdefined ISR.

According to the ISR entry and return code (see below), INTM is neither set nor cleared. Is one of the other exit or return instructions setting or clearing INTM?

Stephen

ISR Entry:

00b79d:   761B        ASP          
00b79e:   FFF0        PUSH         RB
00b79f:   0005        PUSH         AR1H:AR0H
00b7a0:   ABBD        MOVL         *SP++, XT
00b7a1:   A8BD        MOVL         *SP++, XAR4
00b7a2:   A0BD        MOVL         *SP++, XAR5
00b7a3:   C2BD        MOVL         *SP++, XAR6
00b7a4:   C3BD        MOVL         *SP++, XAR7
00b7a5:   E20000BD    MOV32        *SP++, STF
00b7a7:   E20300BD    MOV32        *SP++, R0H
00b7a9:   E20301BD    MOV32        *SP++, R1H
00b7ab:   E20302BD    MOV32        *SP++, R2H
00b7ad:   E20303BD    MOV32        *SP++, R3H
00b7af:   E6300600    SETFLG       RNDF32=1,RNDF64=1
00b7b1:   FF69        SPM          #0
00b7b2:   2942        CLRC         OVM|PAGE0
00b7b3:   5616        CLRC         AMODE

ISR_Exit:

00b7ca:   E2AF03BE    MOV32        R3H, *--SP, UNCF
00b7cc:   E2AF02BE    MOV32        R2H, *--SP, UNCF
00b7ce:   E2AF01BE    MOV32        R1H, *--SP, UNCF
00b7d0:   E2AF00BE    MOV32        R0H, *--SP, UNCF
00b7d2:   E28000BE    MOV32        STF, *--SP
00b7d4:   C5BE        MOVL         XAR7, *--SP
00b7d5:   C4BE        MOVL         XAR6, *--SP
00b7d6:   83BE        MOVL         XAR5, *--SP
00b7d7:   8ABE        MOVL         XAR4, *--SP
00b7d8:   87BE        MOVL         XT, *--SP
00b7d9:   0003        POP          AR1H:AR0H
00b7da:   FFF1        POP          RB
00b7db:   7617        NASP         
00b7dc:   7602        IRET

0 stevenh over 12 years ago in reply to stevenh

Guru 20075 points

Hello,

Could someone at TI please clear up any misunderstanding I may have.

According to page 520, the TRAP instruction transfers control immediately to the ISR. This seems to make it different than a normal hardware interrupt, which waits for INTM to be cleared. Is that correct?

Also, I noticed "clcr INTM" in not in the entry/exit code of either a hardware or a TRAP ISR, so it must be done somewhere else. Where is it done?

Thanks,
Stephen

0 stevenh over 12 years ago in reply to stevenh

Guru 20075 points

Should I have posted this in the C2000 compiler forum?

Stephen

0 stevenh over 12 years ago in reply to stevenh

Guru 20075 points

1. Anything done before "Execute Interrupt Service Routine" (Figure 3.4 or 3.5) is done by the CPU hardware , i.e. Settiing INTM, automatic context save and etc.

2. The Trap instruction is executed immediately after the trap instruction, whether or not the INTM has been cleared.

3. To nest interrupts in a user define trap, the ISR only needs to clear INTM on entry to the ISR.

Stephen

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Nesting of Interrupts in a User Defined Trap ISR