Flactuation in reading of ADC pins A6 A7 B6 B7

Stratis Batzelis

Hi,

I'm using the F28335 control card and trying to utilize the ADC module. I have followed the examples provided by TI, and it seems that the channels A0-5 and B0-5 works fine (reading with 1-2 levels deviation).

However, the values reading from the channels Α6, Α7, Β6 and B7 present significant deviation of the order of 100 levels when I measure a constant DC volatge (eg. a variable potentiometer between Gnd and Vdd=3.3V). Even more strangely, when these pins are left unconnected, they measure an arbitary value but with no deviation!
Moreover, when the provided voltage is very close to 3V, this deviation is eliminated.

So to sum up, when the pins of A6,7 B6,7 are left unconnected --> no deviation

when a DC voltage 3V is applied --> no deviation

when a DC voltage is applied from 0V-2.9V --> significant deviation

This is the setup code:

    // ADCTRL1
   AdcRegs.ADCTRL1.all = 0;
   AdcRegs.ADCTRL1.bit.ACQ_PS = 7;    // freeze window= 8xADCc
   AdcRegs.ADCTRL1.bit.SEQ_CASC =1;    // cascaded sequencer
   AdcRegs.ADCTRL1.bit.CPS = 0;       // divide by 1
   AdcRegs.ADCTRL1.bit.CONT_RUN = 0;   // one shot run mode
   AdcRegs.ADCTRL1.bit.SUSMOD = 0; // do not stop at debug
   // ADCTRL2
   AdcRegs.ADCTRL2.all = 0;
   AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1;   // enable SEQ1 interrupt
   AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 =1;   // SEQ1 start from ePWM_SOCA trigger
   AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0;   // interrupt after every end of sequence
   AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0; // DO NOT Start conversion by software
   // ADCTRL3
   AdcRegs.ADCTRL3.bit.ADCCLKPS = 3;   // ADC clock: FCLK = HSPCLK / 2 * ADCCLKPS
                                       // HSPCLK = 75MHz (see DSP2833x_SysCtrl.c)
                                       // FCLK = 12.5 MHz

I have also tried the codes provided by TI with no difference. It is not a clock issue because I tried very slow reading.

I also tried this in 2 other control card which were available in the lab. Exactly the same results!

Strange? Any ideas?

over 12 years ago

0 Gautam Iyer over 12 years ago

Guru 192875 points

Hi Stratis,

Check with this configuration:

 // Configure ADC
      AdcRegs.ADCMAXCONV.all = 0x0007;       
      AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup ADCINA0 as 1st SEQ1 conv.			
      AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup ADCINA1 as 2nd SEQ1 conv.			
      AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Setup ADCINA2 as 3rd SEQ1 conv.			
      AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Setup ADCINA3 as 4th SEQ1 conv.			
      AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Setup ADCINA4 as 1st SEQ2 conv.			
      AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Setup ADCINA5 as 2nd SEQ2 conv.
	  AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Setup ADCINA6 as 3rd SEQ2 conv.			
      AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7; // Setup ADCINA7 as 4th SEQ2 conv.


     AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1
     AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1;  // Enable SEQ1 interrupt (every EOS)
     AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ2 = 1;// Enable SOCB from ePWM to start SEQ2
     AdcRegs.ADCTRL2.bit.INT_ENA_SEQ2 = 1;  // Enable SEQ2 interrupt (every EOS)

   // Assumes ePWM1 clock is already enabled in InitSysCtrl();
      EPwm1Regs.ETSEL.bit.SOCAEN = 1;        // Enable SOC on A group
      EPwm1Regs.ETSEL.bit.SOCASEL = 1;//4;       // Select SOC from from CPMA on upcount
      EPwm1Regs.ETPS.bit.SOCAPRD = 1;        // Generate pulse on 1st event

 //SOCB
      EPwm1Regs.ETSEL.bit.SOCBEN = 1;        // Enable SOC on B group
      EPwm1Regs.ETSEL.bit.SOCBSEL = 1;//4;       // Select SOC from from CPMB on upcount
      EPwm1Regs.ETPS.bit.SOCBPRD = 1;        // Generate pulse on 1st event

     // EPwm1Regs.CMPA.half.CMPA = 385;	 		 // Set compare A value
      EPwm1Regs.TBPRD = 1501;      			//1501 = 50Khz *********//Set period for ePWM1:15000 = 5KHz -> 200us
      EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;		  // count up and start

Regards,

Gautam

0 Stratis Batzelis over 12 years ago in reply to Gautam Iyer

Prodigy 20 points

Gautam thanks for the response.

As I suspected it is not a timing issue, and not a code-problem at all.

I finally realized that in the control card F28835, the channels Α6,7 and Β6,7 go UNFILTERED to the DSP.

So this is the problem if anyone else is concerned.

0 Gautam Iyer over 12 years ago in reply to Stratis Batzelis

Guru 192875 points

Nice one, Stratis!

Goodluck & Regards,

Gautam

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Flactuation in reading of ADC pins A6 A7 B6 B7