Concerto ADC Vrefhigh impedance

Cameron,

Yeah, you can use a 2.0V reference and then apply a 0 to 2.0V input voltage to the ADC input.

Note that you may have some trouble finding a 2.0V reference, more common would be 2.048V, or you could use one of the very common reference voltages of 2.5V, 3.0V, or 3.3V (and then scale your input voltage accordingly).

The VREFHI pin will have average current draw in the low 100's of uA and transient current draw approaching 1mA (current transients are ADC input dependent and come at a frequency of approximately the ADCCLK). Unfortunately I don't have a detailed design guide for the external reference, but I would recommend that you drive the VREFHI pins using something similar to the following:

Voltage reference IC -> 10uF capacitor -> voltage follower op-amp -> 10uF capacitor -> VREFHI pin

The last 10uF capacitor should be ceramic SMT in the smallest package possible and should be placed as close as possible to the VREFHI pin.

You need to ensure that the op-amp is unity gain stable driving the large capacitive load.  Also consider that the offset voltage of the op-amp will directly contribute to ADC gain error (with 3.3V reference, LSB = 0.8mV, so 1mV of op-amp offset will add just over 1LSB of gain error).   

You should check the initial accuracy and temperature drift of the reference IC, as this will also directly affect ADC gain error.

As far as driving the ADC input using a voltage divider, the device datasheet has an input model of the ADC (for F28M35, this is Fig. 11-12 in the TRM). You should simulate in SPICE (or do a first order RC settling hand calculation) to ensure that Ch (sample and hold capacitor) settles to within at least 1/2 LSB in the allotted S+H time (ACQPS + 1 ADCCLKs).  With a voltage divider, you may need to trade-off using lower resistances (but with a higher static current consumption) to get the RC time constant down.  In addition to the voltage divider resistance, your sensor/voltage source will also have some equivalent series resistance that needs to be factored in. If the resistance ends up being too high, you may need to use an op-amp to drive the ADC input.  

We typically recommend to tie VREFHI to VDDA when using internal reference, but I don't think it particularly matters.

We don't directly spec' an impedance for the ADC inputs, but we do spec a worst case leakage current of 2uA. You can roughly back calculate that the input impedance (assuming 3.3V input gives maximum leakage) is about 1.65M. Typical leakage current will be much lower than this, usually around 500nA.

The ADC input behaves as high impedance when the ADC is not sampling or converting, but when the S+H is open you will have a relatively low impedance path to charge the S+H cap.  Mostly you should do the RC transient analysis that I mentioned in my last post to ensure that your S+H capacitor is charged to 1/2LSB (about 0.01% of final value, 9 RC time constants) in the allotted S+H time.

If the source impedance is high, but the sampling rate on that channel is low, you can add a charge sharing capacitor at the ADC pin to help charge the ADC S+H cap.  This will also create a low pass filter, which may or may not be desirable.  See this app note (not specifically for C2000 ADCs, but still applicable) for more information:

http://www.ti.com/lit/an/spna118b/spna118b.pdf