Hi,
The JTAG chain in our current design has the TMS320F28335 processor along with other JTAG target devices such as FPGA's and CPLD's.
The Processor datasheet says that the processor will be placed in to Emulator mode when EMU1 = 1 at the rising edge of TRST signal.
In our design, the EMU0 and EMU1 of TMS320F28335 are always pulled up to logic HIGH by pullup resistor. There is no possibility to place the processor in to boundary scan mode because the EMU1 pin is hardcoded to logic 1 and it can not be toggled.
The question is,
When the processor is placed in Emulation mode. Is it possible to program other JTAG target devices (FPGA/CPLD) on the same JTAG chain by FPGA/CPLD debugger.
Thank you