• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 82 subscribers
  • Views 386 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC Linearity

Richard Liggiero
Prodigy 50 points

Other Parts Discussed in Thread: TMS320F28377D

Regarding the Errata for TMS320F28377D INL/DNL.

Is there a typical graph illustrating the All Codes INL & DNL for the ADC in both 12 & 16Bit Mode?

I am concerned with the Errata statement of missing codes??

INL/DNL performance does not meet data sheet specifications. For 16-bit mode, typical
performance is: INL = ±12 LSBs, DNL = [+1.5,-1] LSBs. Missing codes are present every
512 codes, in sets of up to 16 missing codes in a row. For 12-bit mode, typical
performance is: INL = ±4 LSB, DNL = [+1, -1] LSBs. Missing codes are present every
128 codes, in sets of up to 4 missing codes in a row.

I believe a detailed view of the all codes capture along with a zoomed in view of the linearity transfer function is required.

  • 0
    TI__Guru 60865 points

    Hi Richard,

    Please find two zoomed in sections of linearity data for INL/DNL both 12-bit and 16-bit mode in the attached presentation.  I think the linearity erratum will make more sense in the context of these data captures.

    8132.F2837xD_Linearity_Rev0.pptx

    Note that this issue is fixed in Rev. A silicon; if you have Rev. 0 devices we can try to get you newer devices where this isn't an issue.

  • 0 in reply to Devin Cottier
    Prodigy 50 points

    Thank you for such a quick response. Exactly what I needed.

    You stated that this is fixed on Rev A silicon, could I also get a similar set of plots demonstrating the corrective

    action as well.

  • 0 in reply to Richard Liggiero
    TI__Guru 60865 points

    I've updated the presentation to include some typical linearity data for Rev. A devices.  Note that the 12-bit data for Rev. 0 is in differential mode, while 12-bit data for Rev. A is single-ended.  We don't intend to guarantee that differential performance > single-ended performance in 12-bit mode (differential mode is required for 16-bit mode), but as you can see from the data this will likely be the case.   

    4555.F2837xD_Linearity_Rev0.pptx

    We have not shipped trimmed devices yet.  If you intend to use 16-bit mode and getting trimmed units gates your development, please contact your FAE/sales rep. to discuss the timeline for when samples with trim will be available.