Watchdog reset [ F28377D ]

Sh.Sasaki

Guru 13625 points

I have a question of F28377D　Watchdog timer.

CPU1 does not Reset when CPU2 WDRST occurs.

How CPU1 can know that CPU2 WDTRS has occurred ?

Regards,

FSSer

0 Vivek Singh over 11 years ago

HI FSSer,

On CPU1 side, there is NMIFLG register which has status bits to indicate if CPU2 NMIWD or WD has triggered.

Let me know if this helps.

Regards,

Vivek Singh

0 Sh.Sasaki over 11 years ago in reply to Vivek Singh

Guru 13625 points

Hi Vivek Singh,

I'm always thankful for the help.

I was convinced to check the register.

Best Regards,

FSSer

0 Jaysun Law over 11 years ago in reply to Vivek Singh

Hi Vivek Singh:

I have got a question that is how can i disable the NMIWD?I have try write 1 to NMICFG Register(NMIE bit), but it doesn't work? I don't konw why?

Regards,

Law

0 Vivek Singh over 11 years ago in reply to Jaysun Law

Hi Jaysun,

Bit NMIE is R/W=1 and wrtting '1' only sets this bit field (not clears) . Once it's set, it can be cleared by "SYSRSn" reset only.

Regards,

Vivek Singh

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