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Simultaneous Sampling in F28377D

dinesh varma
Prodigy 90 points

Hello,

i have quick question.

how many channels can be used for simultaneous sampling on F28377D?

in 16 bit mode, is it four as one from each ADC or can we use every channel(16) for simulataneous

  • 0
    TI__Guru 60865 points

    Hi Dinesh,

    Each ADC allows sampling one channel at a time.  There are 4 ADCs, and they can be triggered by the same or different sources, so you can configure the device to sample up to 4 channels simultaneously (each has to be on a different ADC). It doesn't matter which channels you choose on a given ADC.  

    e.g. you could simultaneously sample A0, B0, C0, D0 or simultaneous sample A2, B4, C3, D4 or you could simultaneously sample A1, B3, and C2, while ADC D runs asynchronously.

  • 0 in reply to Devin Cottier
    Prodigy 90 points

    If i wanna to use 8 channels simultaneously which is not possible because at max we can use only 4..

    So can i simultaneously sample A0, B0, C0, D0 first and with next trigger can i sample simultaneously  A1, B1, C1, D1??

    basically its like for odd sample time it has to sample A0, B0, C0, D0 simultaneously  and for even time A1, B1, C1, D1

     

  • 0 in reply to dinesh varma
    TI__Guru 60865 points

    If you setup A0, A1, B0, B1, C0, C1, D0, D1 to all use the same trigger, then when the trigger occurs A0, B0, C0, D0 will be sampled simultaneously, and then immediately afterwards A1, B1, C1, D1 will be sampled simultaneously (assuming all 4 ADCs are setup in the same resolution and using the same S+H window duration.

  • 0 in reply to Devin Cottier
    Prodigy 90 points

    Hello devin,

    For my application i have to use 8 channels in 16 bit mode.. as per your suggestion i should have same window duration(ACQPS) and as C0,C1 arent there so 

    AdcaRegs.ADCSOC0CTL.bit.CHSEL = 3; //SOC0 will convert ADCINA3
    AdcaRegs.ADCSOC0CTL.bit.ACQPS = 19; //SOC0 will convert with 20 SYSCLK cycle acquisition
    window
    AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 10; //SOC0 will begin conversion on ePWM3 SOCB/D
    AdcbRegs.ADCSOC0CTL.bit.CHSEL = 3; //SOC0 will convert ADCINB3
    AdcbRegs.ADCSOC0CTL.bit.ACQPS = 19; //SOC0 will convert with 20 SYSCLK cycle acquisition
    window
    AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 10; //SOC0 will begin conversion on ePWM3 SOCB/D
    AdccRegs.ADCSOC0CTL.bit.CHSEL = 3; //SOC0 will convert ADCINC3
    AdccRegs.ADCSOC0CTL.bit.ACQPS = 19; //SOC0 will convert with 20 SYSCLK cycle acquisition
    window
    AdccRegs.ADCSOC0CTL.bit.TRIGSEL = 10; //SOC0 will begin conversion on ePWM3 SOCB/D
    AdcdRegs.ADCSOC0CTL.bit.CHSEL = 3; //SOC0 will convert ADCIND3
    AdcdRegs.ADCSOC0CTL.bit.ACQPS = 19; //SOC0 will convert with 20 SYSCLK cycle acquisition
    window
    AdcdRegs.ADCSOC0CTL.bit.TRIGSEL = 10; //SOC0 will begin conversion on ePWM3 SOCB/D

    /// Second simulataeous

    AdcaRegs.ADCSOC0CTL.bit.CHSEL =4; //SOC0 will convert ADCINA4
    AdcaRegs.ADCSOC0CTL.bit.ACQPS = 19; //SOC0 will convert with 20 SYSCLK cycle acquisition
    window
    AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 10; //SOC0 will begin conversion on ePWM3 SOCB/D
    AdcbRegs.ADCSOC0CTL.bit.CHSEL = 4; //SOC0 will convert ADCINB4
    AdcbRegs.ADCSOC0CTL.bit.ACQPS = 19; //SOC0 will convert with 20 SYSCLK cycle acquisition
    window
    AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 10; //SOC0 will begin conversion on ePWM3 SOCB/D
    AdccRegs.ADCSOC0CTL.bit.CHSEL = 4; //SOC0 will convert ADCINC4
    AdccRegs.ADCSOC0CTL.bit.ACQPS = 19; //SOC0 will convert with 20 SYSCLK cycle acquisition
    window
    AdccRegs.ADCSOC0CTL.bit.TRIGSEL = 10; //SOC0 will begin conversion on ePWM3 SOCB/D
    AdcdRegs.ADCSOC0CTL.bit.CHSEL = 4; //SOC0 will convert ADCIND4
    AdcdRegs.ADCSOC0CTL.bit.ACQPS = 19; //SOC0 will convert with 20 SYSCLK cycle acquisition
    window
    AdcdRegs.ADCSOC0CTL.bit.TRIGSEL = 10; //SOC0 will begin conversion on ePWM3 SOCB/D

    will the above set of code work in a way that you mentioned in prev post like when triggered  A3,B3,C3,D3 will sample simultaneously and then followed by A4,B4,C4,D4

  • 0 in reply to dinesh varma
    TI__Guru 60865 points

    Dinesh,

    I think you will want to set the first set of simultaneous conversions to use SOC0 from the 4 respective ADCs and then the second set to use SOC1.  The way you have it now, the first set of configurations are overwritten by the second set.  When both SOC0 and SOC1 have the same trigger, SOC0 will convert first, then SOC1 as soon as SOC0 is complete, which I think is what you want.

    You should also be aware that 16-bit mode uses differential inputs, so you need 2 pins for each input.  These pins are grouped as even/odd channel pairs: e.g. A0/A1 or C2/C3. If you set the channel select to ADC x channel 0 or ADC x channel 1 in 16-bit differential mode, the result will be the same: the pair ADCx0 and ADCx1 will be converted.  To sample 8 channels in two sets, you probably want something like this:

    A0/A1 and B0/B1 and C2/C3 and D0/D1

    then

    A2/A3 and B2/B3 and C4/C5 and D2/D3

    (If you have the 176-pin package that only has 3 inputs on ADC C, you can setup ADC C to convert channels 14/15 which are connected to ADCIN14/15) 

    You could also consider doing something like sampling the first set of channels, then the second set, then the first set again.  You would then average the two samples from the same channel, the result of which should then be coincident in time with the second set of samples. 

  • 0 in reply to Devin Cottier
    Prodigy 90 points


    Thank you devin for a quick reply..

    i am using 176 package.. and i made some changes as per your suggestion. Could you please go through it and please let me know if i have to made any changes and highlighted some lines where i really doubted 

    AdcaRegs.ADCCTL2.bit.RESOLUTION = 1; // 16 bit
    AdcaRegs.ADCCTL2.bit.SIGNALMODE = 1; // differential

    and i will set the same for AdcbRegs, AdccRegs, AdcdRegs


    AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; //A0
    AdcaRegs.ADCSOC0CTL.bit.CHSEL = 1; //A1
    AdcaRegs.ADCSOC0CTL.bit.ACQPS = 19; //SOC0 will convert with 20 SYSCLK cycle acquisition
    AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 9; //SOC0 will begin conversion on ePWM3 SOCA/C

    AdcbRegs.ADCSOC0CTL.bit.CHSEL = 0; //B0
    AdcbRegs.ADCSOC0CTL.bit.CHSEL = 1; //B1
    AdcbRegs.ADCSOC0CTL.bit.ACQPS = 19; //SOC0 will convert with 20 SYSCLK cycle acquisition
    AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 10; //SOC0 will begin conversion on ePWM3 SOCB/D

    AdccRegs.ADCSOC0CTL.bit.CHSEL = 2; //C2
    AdccRegs.ADCSOC0CTL.bit.CHSEL = 3; //C3
    AdccRegs.ADCSOC0CTL.bit.ACQPS = 19; //
    AdccRegs.ADCSOC0CTL.bit.TRIGSEL = 9; //ePWM3 SOCA/C

    AdcdRegs.ADCSOC0CTL.bit.CHSEL = 0; //D0
    AdcdRegs.ADCSOC0CTL.bit.CHSEL = 1; // D1
    AdcdRegs.ADCSOC0CTL.bit.ACQPS = 19; //
    AdcdRegs.ADCSOC0CTL.bit.TRIGSEL = 10; //ePWM3 SOCB/D

    /// Second simulataeous


    AdcaRegs.ADCSOC1CTL.bit.CHSEL =2; //A2
    AdcaRegs.ADCSOC1CTL.bit.CHSEL =3; //A3
    AdcaRegs.ADCSOC1CTL.bit.ACQPS = 19; //
    AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 9; // ePWM3 SOCA/C

    AdcbRegs.ADCSOC1CTL.bit.CHSEL = 2; //B2
    AdcbRegs.ADCSOC1CTL.bit.CHSEL = 3; //B3
    AdcbRegs.ADCSOC1CTL.bit.ACQPS = 19; //
    AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = 10; //ePWM3 SOCB/D

    AdccRegs.ADCSOC1CTL.bit.CHSEL = 14; //ADCIN14
    AdccRegs.ADCSOC1CTL.bit.CHSEL = 15; //ADCIN15
    AdccRegs.ADCSOC1CTL.bit.ACQPS = 19; //
    AdccRegs.ADCSOC1CTL.bit.TRIGSEL = 9; // ePWM3 SOCA/C


    AdcdRegs.ADCSOC1CTL.bit.CHSEL = 2; //D2
    AdcdRegs.ADCSOC1CTL.bit.CHSEL = 3; //D3
    AdcdRegs.ADCSOC1CTL.bit.ACQPS = 19; //
    AdcdRegs.ADCSOC1CTL.bit.TRIGSEL = 10; //ePWM3 SOCB/D

    As per tech document

    When the ePWM3 trigger is received, all four ADCs will begin converting in parallel immediately. All
    results will be in the ADCRESULT0 register for each ADC. Note that this assumes that all ADCs are idle
    when the trigger is received. If one or more ADCs is busy, the samples will not happen at exactly the
    same time.

    in second simultaneous conversion we have to use A1/A2 and ADCIN14 and ADCIN15 and as conversion have to occur at a time how can we save the results of ADCIN14 and ADCIN15 in different register?

  • 0 in reply to dinesh varma
    TI__Guru 60865 points

    Where the conversion results go is based on the SOC used to convert it, not the channel converted.  SOC0 results go to ADCRESULT0, SOC results go to ADCRESULT1, etc.  

    For the trigger select, you don't need to use different ePWMs if you don't want to; you can set all the triggers to be the same.

  • 0 in reply to Devin Cottier
    Prodigy 90 points

    Got it devin, Thank you for your suggestions. My input is only single ended so can i connect all inputs of odd channels to analog Ground?

  • 0 in reply to dinesh varma
    TI__Guru 60865 points

    This won't work; the common mode voltage needs to be within 50mV of (VREFHI + VREFLO)/2.  

    You can use one fully differential op-amp or two single-ended op-amps per-channel to do single-ended to differential conversion.

  • 0 in reply to Devin Cottier
    Prodigy 90 points

    Do we have on board  differential op-amp or single-ended op-amp to differential conversion available or we have to externally?

  • 0 in reply to dinesh varma
    TI__Guru 60865 points

    You have to design these circuits and connect them externally, they aren't included on the ControlCard.