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TMS320F28335 Power Requirements for Flash Programming and Wait States

Paul Joseph
Expert 2795 points

I have two questions regarding power:

What are power needs to satisfy the FLASH programming requirements.

 The second question is the impact of wait states on power.   I could not find any information in the datasheet that gave a way to quantify the impact; examples use data is for running from FLASH and we are expecting to run from SRAM.

Thank you.

  • 0
    Guru 192875 points

    Hi Paul,

    Paul Joseph said:
    What are power needs to satisfy the FLASH programming requirements.

    During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Table 6-67. If the user application involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.

    Paul Joseph said:
     The second question is the impact of wait states on power.   I could not find any information in the datasheet that gave a way to quantify the impact; examples use data is for running from FLASH and we are expecting to run from SRAM.

    When the identical code is run off SARAM, IDD would increase as the code operates with zero wait states.

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    TI__Intellectual 925 points

    Hi Gautam,

    Thanks for answering the questions, regarding the 1st question:

    The data from table 6-67 (flash programming power) to the normal operational currents:

    • VDDIO is lower during programming
    • VDD is lower during programming
    • VDD3VFL is higher during programming

    Could you please confirm that if accommodate the 75mA for VDD3VFL (compare to the normal max of 40mA), that is all. As note (2) from table 6-1 tells to allow the "extra" current indicated in the table 6-67.

    Best regards,

    Max

  • 0 in reply to Xinyu Dai
    Guru 192875 points

    Xinyu Dai said:
    Could you please confirm that if accommodate the 75mA for VDD3VFL (compare to the normal max of 40mA), that is all. As note (2) from table 6-1 tells to allow the "extra" current indicated in the table 6-67.

    That's true! An extra margin has to considered and is supposed to be taken care of.

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    Expert 2795 points

    Okay, just to be clear, is 75mA sufficient margin?

  • 0 in reply to Paul Joseph
    Guru 192875 points

    Paul Joseph said:
    Okay, just to be clear, is 75mA sufficient margin?

    100mA would be suitable.

  • 0 in reply to Xinyu Dai
    TI__Guru* 95315 points

    The number quoted in the datasheet should satisfy both scenarios (code running off flash or SARAM). When you run code off SARAM, it is true the Idd current will be higher , since code is now running with zero waitstates. However, the IDD3VFL current will decrease , since code is not running off flash. The change in current does not quite even out completely, so running code off SARAM would result in a  slight elevation in device power consumption (around 50 mW). Regardless, the number should still stay within the datasheet limits. Note, however, that the I/O loading will be different across designs. So, IDDIO current may be higher in a customer design.