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profile clock cycles are different from one test to other for the same function

piccolo naga
Prodigy 180 points

Other Parts Discussed in Thread: TMS320F28021

hi all

I am using xds100 v2 tool with tms320f28021 controller. at the debug stage, while counting the clock cycles using profile clock, for each iteration the clock count is different for the same function. same function is going to show the clock count differently for each time the test is done. Now i need to perform the timing analysis based on this clock count. if i am not getting the same clock count for the same function for repeated test, how could i perform timing analysis based on clock count.

  • 0
    Guru 192875 points

    Hi PN,

    piccolo naga said:
    Now i need to perform the timing analysis based on this clock count. if i am not getting the same clock count for the same function for repeated test, how could i perform timing analysis based on clock count.

    Which function are you talking about? Let me check the same at my end.

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    Prodigy 180 points

    Good question gautham. 

    it happens mostly at user defined functions. For my application, i have to read adc and send it to PC using SCI. I do use pwm in my application.  

  • 0 in reply to piccolo naga
    Guru 192875 points

    piccolo naga said:
    it happens mostly at user defined functions. For my application, i have to read adc and send it to PC using SCI. I do use pwm in my application.  

    Instead try using CPU timer, this will give you better notable results. Check this link out:

    http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/275225.aspx

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    Prodigy 180 points

    I gone through the link. i do agree with code optimization. But, keeping aside this, my question is why do we get different clock cycle count for the same function(whether it is optimized or not). i am enabling clock from

    debug-> run->clock-> enable clock. were you talking about the same clock.

    Code optimization reduces no of clock cycles. My doubt is not reducing no.of clock cycles, why do i get different clock cycles for the same function which is computed for various times

  • 0 in reply to piccolo naga
    Guru 192875 points

    piccolo naga said:

    debug-> run->clock-> enable clock. were you talking about the same clock.

    Code optimization reduces no of clock cycles. My doubt is not reducing no.of clock cycles, why do i get different clock cycles for the same function which is computed for various times

    At my end clocks for ADC conversion and storing to result register is same. Yes, for SCI communication it varies as per the amount of data to be transmitted.

    Regards,

    Gautam

  • 0
    Prodigy 190 points

    hi， naga。for which function did you test？

    if you use “step over” to test，l wonder if the function go to the interrupt when you test。l suggest you can test the function with “step into”。

    and it is possible for some function that test with diff clock in diff time。for example，SFO（），this function based on the chip running status。so if you test this function ，you will get diff clock in diff time。

  • 0 in reply to hai sun
    Prodigy 180 points

    HI sun ,

    what i observed regarding this is, i am getting same number of clock cycles for certain functions such as initialization functions, library functions, user defined function which doesn't involve ADC calibration or reading data from adc, or external Interrupts. For sci functions clock cycles vary as of your sci data length. make a note on this and try from your side. let me know the results from your side.