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F2812 Power On Sequence (Electrical)

brian gaddis
Prodigy 40 points

The documentation for the F2812 states that when powering up the device the 1.8V should not reach 0.3V until the 3.3V has reached 2.5V.  This is needed to "ensure the reset signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the modules inside the device".

Where does the 0.3V requirement come from?  What are the consequences if this power on sequence is not met (assuming we are holding the reset pin of the processor low (in reset) well beyond the point when both power supplies have come up to their nominal value)?

  • 0
    TI__Guru 61235 points

    Brian,

    Per the F2812 datasheet, SPRS174T, p.98:

    Enable power to all 3.3-V supply pins (VDDIO, VDD3VFL, VDDA1/VDDA2/VDDAIO/AVDDREFBG) and then
    ramp 1.8 V (or 1.9 V) (VDD/VDD1) supply pins.
    1.8 V or 1.9 V (VDD/VDD1) should not reach 0.3 V until VDDIO has reached 2.5 V. This ensures the reset
    signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the
    modules inside the device.

    So it is exactly what it says.  You need the VDDIO to reach 2.5V to ensure that the reset signal from the I/O pin has propogated through the I/O buffer to hold all the internal 1.8/1.9V logic in reset while the 1.8/1.9V supply ramps.  Otherwise, unpredictable behavior can happen if the modules are not held in reset while they power up.

    Regards,

    David