Since the CAN control and status registers have to be accessed 32-bit-wise I need to make sure that the compiler generates only 32-bit accesses to the CAN registers.
I know the examples where shadow structures of the CAN registers are used, but unless really necessary, I don't want to rewrite all our existing code using shadow structures.
My old code does stuff like this:
if (*CANMC & (1L<<11))
boffcnt = 200;
where CANMC is defined as
#define CANMC (volatile long *)0x006014
From the above C code the compiler generates
MOVL XAR4,#2048
MOVL XAR5,#24596
MOVL ACC,XAR4
AND AL,*+XAR5[0]
AND AH,*+XAR5[1]
TEST ACC
MOVB @_boffcnt,#200,NEQ
where the two AND instructions are 16-bit accesses.
I could achieve what I want using
if (*CANMC>>11 & 1)
boffcnt = 200;
which translates to
MOVL XAR4,#24596
SETC SXM
MOVL ACC,*+XAR4[0]
SFR ACC,11
ANDB AL,#0x01
MOVB AH,#0
TEST ACC
MOVB @_boffcnt,#200,NEQ
Here, the "MOVL ACC,*+XAR4[0]" is a 32-bit access, but I don't want to rely on such things unless someone can point me to the documentation, where it is stated that 32-bit accesses are guaranteed that way.
Therefore, I'd like to know whether there is a way to make sure that certain locations in memory are accessed only 32-bit-wise.
Apparently, this works too:
unsigned long tmp = *CANMC;
if (tmp & 1L<<11)
boffcnt = 200;
which translates to
MOVL ACC,*+XAR4[0]
MOVL *-SP[26],ACC
MOVL XAR4,#2048
MOVL ACC,XAR4
AND AL,*-SP[26]
AND AH,*-SP[25]
TEST ACC
MOVB @_boffcnt,#200,NEQ
Here, *CANMC is read in one 32-bit read instruction and stored on the stack. Is it guaranteed that this is the case for all versions of the compiler and all combinations of optimization options? (Currently I'm using version 5.2.3 of the code generation tools.)
Thanks in advance
Johannes
