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ENOB for ADC in piccolo

sunil barot
Intellectual 580 points

Other Parts Discussed in Thread: TMS320F28035

The first release of the TMS320F28035 is going to have "linearity degrades with increasing temperature" issue unresolved. Add to it the datasheet showing

+20 to -20 LSB offset error

+40 to -40 LSB gain error

+4 to -4 LSB variation in gain and offset  from channel to channel

+/- 2 LSB INL and +/- 1 LSB DNL

I do not see anywhere in the datasheet that calibrating the ADC in the software can reduce the error in offset and gain error below the daasheet values mentioned above.

I have following questiions.

1. If I am required to design a power supply that has a guaranteed 1% output than I have to read the output to the accuracy of 0.1 % for example. How can I ensure the feedback to be accurate if I use the ADC that has errors of the magnitude beyond 1 % ?

2. With all the errors taken into account can TI specifiy ENOB  ? Let it be specified under all sorts of test conditions.

I do not know about others but I am very uncomfortable to see such a high degree of gain and offset error unless I get a feedback from TI that I have misunderstood the specifications or there is a way around it.

For comparison here is the error numbers for dsPIC33F series by MIcrochip.

INL = +/- 2

DNL = +/- 1

gain error = min 1.25 to max 10 LSB

offset error = min -0.2 to max 5 LSB

No calibration is required to ensure the specifications.

As anybody can see it the gain and offset error that is way too big in C2000 processors. I looked at many other processors but all of them have few LSB gain and offset errors.

 

  • 0
    TI__Guru* 82910 points

    Sunil,

    Please refer to section 1.8.2 of the ADC UG http://focus.ti.com/lit/ug/spruge5b/spruge5b.pdf  (page 17) on how to remove the offset error of the on-chip ADC.  This can be done without any external hookups via an internal connection to VREFLO signal.

    For gain error, this large variation is due to the use of an internal BG reference, which provides 0-3.3V conversion range always, without any external references.  This is not the case with the dsPIC33F, which requires constnat application of VREFHI/LO for the converter to work.   

    The variation is driven by temperature ~-50ppm/degC which equates to ~0.005% gain error change per degree C.  The value of 40 represents the gain error in terms of LSB at the Full scale range of the device, at half scale(1.65V) this would only be 20LSB, etc.  So, if your end use condition does not have the full -40C to 125C temp range, this movement is less.

    The difference in the dsPIC device, is it is quoting the gain error with an assumed perfect VREFHI/LO referernce; passing this limitation to your system.

    To be clear there is also a VREFHI/LO supported mode for 28035, which has +/-20LSB of gain error with ideal VREFHI/LO.

    To address the errata we are working on a silicon revision to address the linearity limitation you have mentioned.  We hope to have data on this soon.

    Please let me know if this helps clarify your questions/concerns.

    Best,

    Matthew

     

  • 0 in reply to MatthewPate
    Intellectual 580 points

    Matthew,

    Thank you for the clarification.

    1. Offset error

    According to you and accroding to the section 1.8.2 in the ADC datasheet can I say that the offset error can be brought down to almost 0 LSB if "AdcOffsetSelfCal()" function is called on regular basis to take care of any variation in the offset due to variation in the temperature ? is there any other cause of the offset error that cannot be compensated by the calibration ?

    2. Gain error

    We are using external reference. The maximum gain error caused by the ADC is specified to be + 40 LSB to - 40 LSB in TMS320F28035 and not +20 LSB to -20 LSB that you refer to. Is the gain error always tied to the temperature by the -50ppm/degC relation ? Can we compensate for the gain error by using internal temperature sensor and compensate both for temperature variation and the amplitude of the signal ? For example if the signal is at full scale and the temperature is 125 C the gain error can be reduced to 0 LSB if 40 LSB is subtracted from the result. Ofcourse we have to account for the error in the reading of the temprature and the amplitude but the numbers are mentioned to simplify the understanding.

    Let us say that we can trim the errors by calibration and compensation as mentioned above. What is the most resonable stacked up error in terms of LSB 's that we are dealing with here ?

    One last question. How much  is the degradation expected in the linearity with temperature in the first version of the chip ?  Do you have some estimate in terms of LSB ?