A2D Results Register

On TMS320F28035 - I am seeing analog signal of ADCINA0 shows up in ADCRESULT1; ADCINA2 shows up in ADCRESULT3;  ADCINA4 shows up in ADCRESULT5; etc.  There are no problems with this same software on TMS320F28035 micros that we purchased a couple of years ago, but the micros that we purchased recently are exhibiting this.  Please help.

Mark,

I believe what you are seeing is described in the errata below.  You will have to add one of the workarounds to avoid this condition.  This is from page 10 of SPRZ295I(errata).  This is a timing related bug, so there are going to be devices that show/don't show the condition over all operational conditions.  This explains why some devices you had did not show this.

Advisory ADC: ADC Result Conversion When Sampling Ends on 14th Cycle of Previous
Conversion, ACQPS = 6 or 7
Revision(s) Affected 0, A
Details The on-chip ADC takes 13 ADC clock cycles to complete a conversion after the
sampling phase has ended. The result is then presented to the CPU on the 14th cycle
post-sampling and latched on the 15th cycle into the ADC result registers. If the next
conversion's sampling phase terminates on this 14th cycle, the results latched by the
CPU into the result register are not assured to be valid across all operating conditions.
Workaround(s) Some workarounds are as follows:
• Due to the nature of the sampling and conversion phases of the ADC, there are only
two values of ACQPS (which controls the sampling window) that would result in the
above condition occurring—ACQPS = 6 or 7. One solution is to avoid using these
values in ACQPS.
• When the ADCNONOVERLAP feature (bit 1 in ADCTRL2 register) is used, the above
condition will never be met; so the user is free to use any value of ACQPS desired.
• Depending on the frequency of ADC sampling used in the system, the user can
determine if their system will hit the above condition if the system requires the use of
ACQPS = 6 or 7. For instance, if the converter is continuously converting with
ACQPS = 6, the above condition will never be met because the end of the sampling
phase will always fall on the 13th cycle of the current conversion in progress.

Thank you for the quick response.  I replaced ACQPS = 7 with ACQPS = 8 and that avoids the issue.