Other Parts Discussed in Thread: TMS320F28377D
Hi All,
I'm evaluating a TMS320F28377D controller card and I'm having some differences I can't explain.
I'm using ADCA and ADCB with Systemclock 200MHz, ADC clocks on 50MHz in 16bit mode (identical configurations).
The sample-rate is about 1MSPS on both converters and each converters is sampling a fixed channel in burstmode, triggered by a PWM source.
When I take a look at the results of both ADC, which have the same configuration, the histogram of ADCA is 2x worse than ADCB. How comes!? Both analog channels are tied to ground (bridged the analogue decoupling capacitors on the controller card).
Best regards.
| EALLOW; AdcaRegs.ADCCTL2.bit.PRESCALE = (ADC_PRESCALE -1)*2; //set ADCCLK divider to /4 by value 6. AdcaRegs.ADCCTL2.bit.RESOLUTION = RESOLUTION_16BIT; AdcaRegs.ADCCTL2.bit.SIGNALMODE = SIGNAL_DIFFERENTIAL; AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1; //Set pulse positions to late AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; //power up the ADC udelay(1000); //delay for 1ms to allow ADC time to power up EDIS; acqps = 14; //75ns for 12bit if(RESOLUTION_16BIT == AdcaRegs.ADCCTL2.bit.RESOLUTION) //determine minimum acquisition window (in SYSCLKS) based on resolution acqps = 75; //>320ns for 16bit EALLOW; AdcaRegs.ADCBURSTCTL.bit.BURSTEN = 1; //Enable ADC burst mode AdcaRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = ePWM1_ADCSOC_AC; //PWM1 will trigger burst of conversions AdcaRegs.ADCBURSTCTL.bit.BURSTSIZE = 10-1; //conversion bursts n+1 conversions long AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY=6; //15-AdcbRegs.ADCBURSTCTL.bit.BURSTSIZE // AdcaRegs.ADCSOC0CTL.bit.CHSEL = 2; //SOC will convert on channel // AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1; //SOC will convert on channel // AdcaRegs.ADCSOC2CTL.bit.CHSEL = 4; //SOC will convert on channel // AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3; //SOC will convert on channe // AdcaRegs.ADCSOC4CTL.bit.CHSEL = 14; //SOC will convert on channel // AdcaRegs.ADCSOC5CTL.bit.CHSEL = 5; //SOC will convert on channel AdcaRegs.ADCSOC6CTL.bit.CHSEL = 2; //SOC will convert on AdcaRegs.ADCSOC7CTL.bit.CHSEL = 2; //SOC will convert on 3 AdcaRegs.ADCSOC8CTL.bit.CHSEL = 2; //SOC will convert on 3 AdcaRegs.ADCSOC9CTL.bit.CHSEL = 2; //SOC will convert on 3 AdcaRegs.ADCSOC10CTL.bit.CHSEL = 2; //SOC will convert on 3 AdcaRegs.ADCSOC11CTL.bit.CHSEL = 2; //SOC will convert on 3 AdcaRegs.ADCSOC12CTL.bit.CHSEL = 2; //SOC will convert on 3 AdcaRegs.ADCSOC13CTL.bit.CHSEL = 2; //SOC will convert on 3 AdcaRegs.ADCSOC14CTL.bit.CHSEL = 2; //SOC will convert on 3 AdcaRegs.ADCSOC15CTL.bit.CHSEL = 2; //SOC will convert on 3 AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC1CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC2CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC3CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC4CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC5CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC6CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC7CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC8CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC9CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC10CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC11CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC12CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC13CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC14CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCSOC15CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles AdcaRegs.ADCINTSEL1N2.bit.INT1E = 0; //disable INT1 flag AdcaRegs.ADCINTSEL1N2.bit.INT2E = 1; //disable INT2 flag AdcaRegs.ADCINTSEL3N4.bit.INT3E = 0; //disable INT3 flag AdcaRegs.ADCINTSEL3N4.bit.INT4E = 0; //disable INT4 flag AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 0; AdcaRegs.ADCINTSEL1N2.bit.INT2CONT = 1; AdcaRegs.ADCINTSEL3N4.bit.INT3CONT = 0; AdcaRegs.ADCINTSEL3N4.bit.INT4CONT = 0; AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 15; //end of SOC6 will set INT1 flag AdcaRegs.ADCINTSEL1N2.bit.INT2SEL = 15; //end of SOC14 will set INT2 flag AdcaRegs.ADCINTSEL3N4.bit.INT3SEL = 15; //end of SOC7 will set INT3 flag AdcaRegs.ADCINTSEL3N4.bit.INT4SEL = 15; //end of SOC15 will set INT4 flag //ADCINT2 will trigger 16 SOCs AdcaRegs.ADCINTSOCSEL1.bit.SOC0 = 0; AdcaRegs.ADCINTSOCSEL1.bit.SOC1 = 0; AdcaRegs.ADCINTSOCSEL1.bit.SOC2 = 0; AdcaRegs.ADCINTSOCSEL1.bit.SOC3 = 0; AdcaRegs.ADCINTSOCSEL1.bit.SOC4 = 0; AdcaRegs.ADCINTSOCSEL1.bit.SOC5 = 0; AdcaRegs.ADCINTSOCSEL1.bit.SOC6 = 0; AdcaRegs.ADCINTSOCSEL1.bit.SOC7 = 0; AdcaRegs.ADCINTSOCSEL2.bit.SOC8 = 0; AdcaRegs.ADCINTSOCSEL2.bit.SOC9 = 0; AdcaRegs.ADCINTSOCSEL2.bit.SOC10 = 0; AdcaRegs.ADCINTSOCSEL2.bit.SOC11 = 0; AdcaRegs.ADCINTSOCSEL2.bit.SOC12 = 0; AdcaRegs.ADCINTSOCSEL2.bit.SOC13 = 0; AdcaRegs.ADCINTSOCSEL2.bit.SOC14 = 0; AdcaRegs.ADCINTSOCSEL2.bit.SOC15 = 0; |
