Hi,
Sorry for my asking, but there is no example to follow, and I found nothing by my self-study. I need to know how to use the ADC's interrupt to trigger the DMA.
Some of my codes:
------------
// Map ISR functions.
EALLOW;
PieVectTable.ADCA1_INT = &adca1_isr; //function for ADCA interrupt 1
EDIS;
// enable PIE interrupt
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // interrupt of ADC
// Enable global Interrupts and higher priority real-time debug events:
IER |= M_INT1; // Enable group 1 interrupts
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global real-time interrupt DBGM
...
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // end of SOC0 will set INT1 flag
....
interrupt void adca1_isr(void)
{
...
}
-------------------
Above is the configure of ADC, and each time the ADC interrupt can work very well.
------------------
void DMA_configure(void)
{
EALLOW;
CpuSysRegs.SECMSEL.bit.VBUS32_1 = 1;
EDIS;
/*for (i=0; i < RESULTS_BUFFER_SIZE; i++) {
DMABuf1[i] = AdcaResultRegs.ADCRESULT0; // Initialize Buffer;
}
*/
DMAInitialize();
/*
DmaRegs.DMACTRL.bit.HARDRESET = 1; // Perform a hard reset on DMA
__asm (" nop"); // one NOP required after HARDRESET
DmaRegs.DEBUGCTRL.bit.FREE = 1; // Allow DMA to run free on emulation suspend
*/
// Initialize the DMA
// DMA Source is buffer 2, destination is buffer 1
DMA1Source = &AdcaResultRegs.ADCRESULT0;
DMA1Dest = &DMABuf1[0]; //DMA destination;
DMACH1AddrConfig(DMA1Dest,DMA1Source);
/*
// Set up SOURCE address:
DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)&AdcMirror.ADCRESULT0; // Point to beginning of source buffer
DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)&AdcMirror.ADCRESULT0;
// Set up DESTINATION address:
DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)&DMABuf1[0][0]; // Point to beginning of destination buffer
DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)&DMABuf1[0][0];
*/
// Set up to use 16-bit data size
// Pointers are based on 16-bit words
// Increment by 1 (16 16-bit words)
DMACH1BurstConfig(ONE_WORD_BURST,SOURCE_NO_ADDRESS_CHANGE,DESTINATION_INCREMENT_ONE_ADDRESS); // BURST size = 1 | Source step size = 0 | Dest step size += 1
/*
// Set up BURST registers:
DmaRegs.CH1.BURST_SIZE.all = NumberOfChan-1;//Number of words(X-1)x-ferred in a burst
DmaRegs.CH1.SRC_BURST_STEP = 1; // Increment source addr between each word x-ferred
DmaRegs.CH1.DST_BURST_STEP = NumberOfSamples; // Increment dest addr between each word x-ferred
*/
DMACH1TransferConfig(TRANSFER_SIZE_0x800,TRANSFER_STEP_SOURCE_NO_CHANGE,TRANSFER_STEP_DEST_INCREMENT_ONE_ADDRESS); // Transfer size = 0x1000 | Source step size = 0 | Dest step size += 1
/*
// Set up TRANSFER registers:
DmaRegs.CH1.TRANSFER_SIZE = NumberOfSamples-1;//(NumberOfSamples-1); // Number of bursts per transfer, DMA interrupt will occur after completed transfer
DmaRegs.CH1.SRC_TRANSFER_STEP = 1;// TRANSFER_STEP is ignored when WRAP occurs
DmaRegs.CH1.DST_TRANSFER_STEP = 0;// TRANSFER_STEP is ignored when WRAP occurs
*/
DMACH1WrapConfig(0xFFFF,0,0xFFFF,0);
/*
// Set up WRAP registers: wrap on 4 reads of ADC
DmaRegs.CH1.SRC_WRAP_SIZE = NumberOfChan-1; // Wrap source address after N bursts
DmaRegs.CH1.SRC_WRAP_STEP = 0; // Step for source wrap
DmaRegs.CH1.DST_WRAP_SIZE = 0; // Wrap destination address after N bursts
DmaRegs.CH1.DST_WRAP_STEP = 1; // Step for destination wrap
*/
PieVectTable.DMA_CH1_INT = &local_DMACH1_ISR;
// DMA_ADCAINT1 as peripheral interrupt source
DMACH1ModeConfig(DMA_ADCAINT1,PERINT_ENABLE,ONESHOT_DISABLE,CONT_ENABLE,SYNC_ENABLE,SYNC_SRC,OVEFLOW_ENABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE);
/*
Select Value (8-bit) DMA ChTrigger Source
0 No Peripheral
1 ADCA.1
2 ADCA.2
3 ADCA.3
4 ADCA.4
5 ADCAEVT
6 ADCB.1
7 ADCB.2
8 ADCB.3
9 ADCB.4
10 ADCBEVT
11 ADCC.1
12 ADCC.2
13 ADCC.3
14 ADCC.4
15 ADCCEVT
16 ADCD.1
17 ADCD.2
18 ADCD.3
19 ADCD.4
20 ADCDEVT
DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_SEQ1INT; // Passed DMA channel as peripheral interrupt source
DmaRegs.CH1.MODE.bit.PERINTE = PERINT_ENABLE; // Peripheral interrupt enable
DmaRegs.CH1.MODE.bit.ONESHOT = ONESHOT_DISABLE; // Oneshot disable
DmaRegs.CH1.MODE.bit.CONTINUOUS = CONT_ENABLE; // Continous enable
DmaRegs.CH1.MODE.bit.SYNCE = SYNC_ENABLE; // Peripheral sync enable/disable
DmaRegs.CH1.MODE.bit.SYNCSEL = SYNC_SRC; //Sync effects source or destination
DmaRegs.CH1.MODE.bit.OVRINTE = OVEFLOW_ENABLE;//Enable/disable the overflow interrupt
DmaRegs.CH1.MODE.bit.DATASIZE = SIXTEEN_BIT; // 16-bit/32-bit data size transfers
DmaRegs.CH1.MODE.bit.CHINTMODE = CHINT_END; // Generate interrupt to CPU at end of transfer
DmaRegs.CH1.MODE.bit.CHINTE = CHINT_ENABLE; // Channel Interrupt to CPU enable
// Clear any spurious flags:
DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
// Enable DMA INTn in the PIE: Group 7 __interrupt 1-6
PieCtrlRegs.PIEIER7.bit.INTx1 = 1; //DMACH1 interrupt
// Enable CPU INT7 interrupts are enabled
IER |= M_INT7; // interrupt group 7
*/
StartDMACH1();
/*
EALLOW;
DmaRegs.CH1.CONTROL.bit.RUN = 1; // StartDMACH1();
EINT;
*/
}
__interrupt void local_DMACH1_ISR(void)
{
DMA_Done = 0x0001;
EALLOW;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
EDIS;
ESTOP0;
}
----------------
Above is the DMA part. I called the "DMA_configure()" in "main()" function; each time, when the ADC gets the data, it will trigger interrupt function "adca1_isr()" to save data, but the DMA part never works.
Someone asked a similar question in the community, and the advice he got was to study "sdfm_filter_sync_dma_cpu01.c", which didn't do help to me about my problem.
Thanks so much if anyone can help.
