TMS320F28377D errorsts

Is no one able to explain this in more detail? Before depending on this feature I would like to have the feature verified.

Hi Tjarco,

The details of the errorsts pin can be found in the TRM spruhm8b in section 2.5.8.  The NMISHDFLG register (p. 208) is tied to this pin for both CPUs.

The rail voltages for operational level are as spec'd in the datasheet.  Operation of the device is not guaranteed at any voltage out of the DS spec.

Best Regards,

Adam

Hi Adam,

Thanks for your reply. I meant: What is included as "Voltage rails".

Are this all power supply rails, so including: VDD and VDDA and VDDIO and VDD3VFL?

Meaning: I don't have to use an external brownout circuit?

Best regards.

Hi Tjarco,

This pin does not report errors for the supply rails.  There is no internal BOR for any of the power rails, so it is necessary to for external SVS if you want to monitor the rail voltages.

Best Regards,
Adam

Hi Adam,

"The error pin will be tri-stated till the chip power rails ramp up to operational limit"

If I pull down the Error Pin to ground with ~10K, and use it to reset the CPU while the power rail is not within operational limits  or while there are internal errors, then I would have an brown-out and conditional hardware reset, right?

Best regards

Hi Tjarco,

This pin is not meant to be used to monitor or assert a reset based off of the supply rail voltages.  The behavior of this pin is the same as all IOs as they are tri-stated until the rails are operational.

The only way to ensure that XRSn is held low until the rails are operational is to monitor the actual power rails themselves with SVS devices.

Best Regards,

Adam