single phase Phase Locked Loop (PLL) for grid connected output

Dear Manish,

I am doing single phase grid tie inverter  project i am getting struggle in to generate PLL.

When i referred that link http://e2e.ti.com/support/microcontrollers/c2000/f/171/p/118563/690392.aspx  i implemented that code snippet in my project,but i did not PLL output .

How to simulate the theta value in CCS studio using graph window

I will attach the code please help to solve the problem.

#include "F2806x_Device.h"
#include "Solar_IQ.h"
#include "3414.SPLL_1ph.h"

#define table_size 1024 //size of table=1024


#define GRID_FREQ    60
#define PI 3.141592653589
#define ISR_FREQUENCY 50000.0

#define B0_LPF (166.7618719)
#define B1_LPF (-166.4785831)
#define A1_LPF (-1.0)

//SPLL_1ph_IQ spll1;
SPLL_1ph spll1;

_iq15 InvSine;
_iq15 theta;
_iq15 sen_theta;
Uint16 ConversionCount;
int32 Vac_in,Vac_FB;
int32 Offset_Volt;
int32 phase_diff;

//SPLL_1ph_IQ_NOTCH_COEFF spll_notch_coef1;

// Prototype statements for functions found within this file.
__interrupt void cpu_timer0_isr(void);

extern void InitSysCtrl(void);
extern void InitPieVectTable(void);
extern void InitPieCtrl(void);

/*signed int sin_table[64]={0,25,49,73,96,118,137,
159,177,193,208,220,231,239,245,249,250,249,245,
239,231,220,208,193,177,159,137,118,96,73,49,25,0,-25,-49,-73,-96,-118,-137,
-159,-177,-193,-208,-220,-231,-239,-245,-249,-250,-249,-245,
-239,-231,-220,-208,-193,-177,-159,-137,-118,-96,-73,-49,-25};*/

/*signed int sin_table[32]={0,25,49,73,96,118,137,
159,177,193,208,220,231,239,245,249,250,249,245,
239,231,220,208,193,177,159,137,118,96,73,49,25};*/
float c2, c1;
float sin_table[108]={0,0.1736,0.3420,0.5,0.6427,0.7660,0.8660,0.9396,0.9848,1,
        0.9848,0.9396,0.8660,0.7660,0.6427,0.5,0.3420,0.1736,0,-0.1736,-0.3420,
        -0.5,-0.6427,-0.7660,-0.8660,-0.9396,-0.9848,-1,-0.9848,-0.9396,-0.8660,
        -0.7660,-0.6427,-0.5,-0.3420,-0.1736,0,0.1736,0.3420,0.5,0.6427,0.7660,0.8660,0.9396,0.9848,1,
        0.9848,0.9396,0.8660,0.7660,0.6427,0.5,0.3420,0.1736,0,-0.1736,-0.3420,
        -0.5,-0.6427,-0.7660,-0.8660,-0.9396,-0.9848,-1,-0.9848,-0.9396,-0.8660,
        -0.7660,-0.6427,-0.5,-0.3420,-0.1736,0,0.1736,0.3420,0.5,0.6427,0.7660,0.8660,0.9396,0.9848,1,
        0.9848,0.9396,0.8660,0.7660,0.6427,0.5,0.3420,0.1736,0,-0.1736,-0.3420,
        -0.5,-0.6427,-0.7660,-0.8660,-0.9396,-0.9848,-1,-0.9848,-0.9396,-0.8660,
        -0.7660,-0.6427,-0.5,-0.3420,-0.1736};


//RAMPGEN_IQ rgen1;
SPLL_1ph_SOGI_IQ spll2;

_iq21 inv_meas_vol_inst;
_iq24 InvSine;

char index = 0;


void main(void)
{
    InitSysCtrl();

    DINT;
    InitPieCtrl();
    IER = 0x0000;
    IFR = 0x0000;
    InitPieVectTable();

    EALLOW;  // This is needed to write to EALLOW protected registers
    PieVectTable.TINT0 = &cpu_timer0_isr;
    EDIS;    // This is needed to disable write to EALLOW protected registers

    EALLOW;
    GpioCtrlRegs.GPADIR.bit.GPIO31 = 1;
    GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;
    EDIS;

    InitCpuTimers();   // For this example, only initialize the Cpu Timers
    ConfigCpuTimer(&CpuTimer0,90,50);

    CpuTimer0Regs.TCR.all = 0x4001;

    PieCtrlRegs.PIEIER1.bit.INTx7 = 1;

    IER |= M_INT1;

    EINT;
    ERTM;

    GpioDataRegs.GPASET.bit.GPIO31 = 1;
    GpioDataRegs.GPBSET.bit.GPIO34 = 1;

    // SPLL 1ph Notch Filter Method intialization
        //SPLL_1ph_IQ_init(GRID_FREQ, _IQ21((float)(1.0/ISR_FREQUENCY)), &spll1);

        spll1.lpf_coeff.B0_lf = _IQ21(B0_LPF);
        spll1.lpf_coeff.B1_lf = _IQ21(B1_LPF);
        spll1.lpf_coeff.A1_lf = _IQ21(A1_LPF);

        c1 = 0.1;
        c2 = 0.00001;
        SPLL_1ph_init(60,_IQ21(0.00005),&spll1);
        //SPLL_1ph_IQ_notch_coeff_update(((float) (1.0 / ISR_FREQUENCY)),(float) (2 * PI * GRID_FREQ * 2), (float) c2, (float) c1, &spll1);

    //SPLL_1ph_IQ_init(GRID_FREQ,_IQ21((float)(1.0/ISR_FREQUENCY)),&spll1);
    //SPLL_1ph_IQ_notch_coeff_update(((float)(1.0/ISR_FREQUENCY)),(float)(2*PI*GRID_FREQ*2),(float)0.00001,(float)0.1,&spll1);
        Offset_Volt=_IQ21(0.5); // the input sinusoid is offset with 1.65 V
        phase_diff = 20;

// Step 6. IDLE loop. Just sit and loop forever (optional):
   for(;;)
    {

       ;


    }
}

__interrupt void cpu_timer0_isr(void)
{
   CpuTimer0.InterruptCount++;
   GpioDataRegs.GPBTOGGLE.bit.GPIO34 = 1; // Toggle GPIO34 once per 50 MICROseconds

   spll1.AC_input=(long)sin_table[index] >> 3;;
   SPLL_1ph_run(&spll1);
   InvSine = (long)(spll1.sin[0])>>6; // InvSine is in Q15
   theta = (long)((long)(spll1.theta[0])>>6)+_IQ15(phase_diff); //theta is in Q15


   /*spll1.AC_input=(long)sin_table[index] >> 3;
   //spll1.AC_input=(long)inv_meas_vol_inst>>3;
   SPLL_1ph_IQ_MACRO(spll1);
   InvSine     = (long)(spll1.sin)>> 3; */// InvSine is in Q24
   /*index++;
   if(index > 107)
   {
       index = 0;
   }*/


   // Acknowledge this interrupt to receive more interrupts from group 1
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}