Other Parts Discussed in Thread: TMS320F28335, CONTROLSUITE
Background: Designing digital guitar effects on the TMS320F28335. I have to sample in a guitar signal (currently using onboard ADC), process it, then transfer out to a DAC via SPI. This is a NON/BIOS project. The development board I am using was built by one of my professors. It is set up initially to boot from SCI. I'm sampling at 44.1 kHz through the use of Timer0, I know this isn't the greatest way to do it but it was a quick hack that got me going and I have yet to change it. Prior to my attempt at programming it to flash, the system was working 100% the way I was expecting it too and has been for about a month. The output from the guitar was extremely clean.
The Issue: I made the decision to program it to flash. I followed the SPRA958l document very closely. I've set my initialization routines to run in flash and all of my heavy computational stuff I've copied to RAM via memcpy with the secureRamFunc label the spra958l project provided. But, when the code is executed, the output from the guitar was extremely robotic. I then fed in a signal generator to the ADC input and watched the output through my DAC. It started to distort around 100 Hz, which is silly because I should be sampling at 44.1 kHz. So I decided to run the program all in RAM again and the output was still very robotic. I cannot stress enough that I modified 0 lines of code when I was trying to program the flash memory except for the linker files and #pragma sections for my functions. Everything else with my system runs fine: Interrupts from user input, printing out to LCD screen, FFT analysis and the effects that I have programmed so far.
Debugging: I did notice that some of the initialization code in the spra958l was a little different than mine. I've made sure the initialization that I originally had prior to flash programming is now in the flash programming project. This includes ADC, SPI, TIMER0, XINT initialization.
What I Think is Happening: This is honestly my first attempt at understanding linker files, as embarrassing as that is to admit. But I think the linker files used in spra958l modified registers that don't get reprogrammed when reverting back to non-flash linker file. I could be completely off base with that thought, but I've literally exhausted myself trying to figure this out and that's the only thing I have left to think. I've included the original linker file and the spra958l linker files below.
I didn't include any of my source code and initializations because there is quite a number of them and I didn't want to overload this post unless absolutely necessary. If you want to see any other pieces of code I will be more than happy to share.
I don't have a boot mode switch, only jumpers. When programming to flash, boot mode was set to 0000 which is SCI. After the programming was successful, I then jumpered the pins to set it to 1111. This may be incorrect, its possible i need to jumper first before programming.
Thank you in advance for anyone who sat through this and put in time to help. If there is any other info you would like me to include let me know.
Original Linker provided by University
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SRAM" bootloader mode */
/* BOOT_RSVD is used by the boot ROM for stack. */
/* This section is only reserved to keep the BOOT ROM from */
/* corrupting this area during the debug process */
BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0
RAML0 : origin = 0x008000, length = 0x001000
RAML1 : origin = 0x009000, length = 0x001000
RAML2 : origin = 0x00A000, length = 0x001000
RAML3 : origin = 0x00B000, length = 0x001000
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
ADC_CAL : origin = 0x380080, length = 0x000009
RESET : origin = 0x3FFFC0, length = 0x000002
IQTABLES : origin = 0x3FE000, length = 0x000b50
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000
RAML5 : origin = 0x00D000, length = 0x001000
RAML6 : origin = 0x00E000, length = 0x001000
RAML7 : origin = 0x00F000, length = 0x001000
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
}
SECTIONS
{
/* Setup for "boot to SARAM" mode:
The codestart section (found in DSP28_CodeStartBranch.asm)
re-directs execution to the start of user code. */
codestart : > BEGIN, PAGE = 0
ramfuncs : > RAML0, PAGE = 0
.text : > RAML1, PAGE = 0
/* .cinit : > RAML0, PAGE = 0 */
/* .pinit : > RAML0, PAGE = 0 */
.switch : > RAML0, PAGE = 0
.data : > RAML2, PAGE = 0 /* KG added line */
.bss : > RAML3, PAGE = 0 /* KG added line */
.stack : > RAMM1, PAGE = 1
.ebss : > RAML4, PAGE = 1
.econst : > RAML5, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > RAML1, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
/* DMARAML4 : > RAML4, PAGE = 1 */
/* DMARAML5 : > RAML5, PAGE = 1 */
/* DMARAML6 : > RAML6, PAGE = 1 */
/* DMARAML7 : > RAML7, PAGE = 1 */
ZONE7DATA : > ZONE7B, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */
csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/**********************************************************************
* File: F28335_nonBIOS_flash.cmd -- Linker command file for DSP/BIOS * code with DSP in jump-to-flash boot mode. * * History: * 01/20/11 - Deleted unneeded Boot ROM memory definitions. (D. Alter) * 09/18/07 - original (D. Alter) **********************************************************************/ MEMORY { PAGE 0: /* Program Memory */ BEGIN_M0 : origin = 0x000000, length = 0x000002 /* Part of M0SARAM. Used for "Boot to M0" bootloader mode. */ L0123SARAM : origin = 0x008000, length = 0x004000 /* L0 - L3 SARAM combined, CSM secure */ FLASH_ABCDEFGH (R) : origin = 0x300000, length = 0x03FF80 /* On-chip FLASH */ CSM_RSVD (R) : origin = 0x33FF80, length = 0x000076 /* Part of FLASH Sector A. Reserved when CSM is in use. */ BEGIN_FLASH (R) : origin = 0x33FFF6, length = 0x000002 /* Part of FLASH Sector A. Used for "Jump to flash" bootloader mode. */ PASSWORDS (R) : origin = 0x33FFF8, length = 0x000008 /* Part of FLASH Sector A. CSM password locations. */ OTP (R) : origin = 0x380400, length = 0x000400 /* OTP */ IQTABLES (R) : origin = 0x3FE000, length = 0x000B50 /* Part of Boot ROM */ IQTABLES2 (R) : origin = 0x3FEB50, length = 0x00008C /* Part of Boot ROM */ FPUTABLES (R) : origin = 0x3FEBDC, length = 0x0006A0 /* Part of Boot ROM */ RESET (R) : origin = 0x3FFFC0, length = 0x000002 /* part of Boot ROM */ PAGE 1 : /* Data Memory */ M0SARAM : origin = 0x000002, length = 0x0003FE /* M0 SARAM */ M1SARAM : origin = 0x000400, length = 0x000400 /* M1 SARAM */ L4SARAM : origin = 0x00C000, length = 0x001000 /* L4 SARAM, DMA accessible, 1 WS prog access */ L5SARAM : origin = 0x00D000, length = 0x001000 /* L5 SARAM, DMA accessible, 1 WS prog access */ L6SARAM : origin = 0x00E000, length = 0x001000 /* L6 SARAM, DMA accessible, 1 WS prog access */ L7SARAM : origin = 0x00F000, length = 0x001000 /* L7 SARAM, DMA accessible, 1 WS prog access */ } SECTIONS { /*** Compiler Required Sections ***/ /* Program memory (PAGE 0) sections */ .text : > FLASH_ABCDEFGH, PAGE = 0 .cinit : > FLASH_ABCDEFGH, PAGE = 0 .const : > FLASH_ABCDEFGH, PAGE = 0 .econst : > FLASH_ABCDEFGH, PAGE = 0 .pinit : > FLASH_ABCDEFGH, PAGE = 0 .reset : > RESET, PAGE = 0, TYPE = DSECT /* We are not using the .reset section */ .switch : > FLASH_ABCDEFGH, PAGE = 0 /* Data Memory (PAGE 1) sections */ .bss : > L4SARAM, PAGE = 1 .ebss : > L4SARAM, PAGE = 1 .cio : > L4SARAM, PAGE = 1 .stack : > M1SARAM, PAGE = 1 .sysmem : > L4SARAM, PAGE = 1 .esysmem : > L4SARAM, PAGE = 1 /*** User Defined Sections ***/ codestart : > BEGIN_FLASH, PAGE = 0 /* Used by file CodeStartBranch.asm */ csm_rsvd : > CSM_RSVD, PAGE = 0 /* Used by file Passwords.asm */ internalMemFuncs : > FLASH_ABCDEFGH, PAGE = 0 /* Used by file Xintf.c. Link to internal memory */ passwords : > PASSWORDS, PAGE = 0 /* Used by file Passwords.asm */ secureRamFuncs : LOAD = FLASH_ABCDEFGH, PAGE = 0 /* Used by file Flash.c */ RUN = L0123SARAM, PAGE = 0 /* Load to flash, run from CSM secure RAM */ LOAD_START(_secureRamFuncs_loadstart), LOAD_SIZE(_secureRamFuncs_loadsize), RUN_START(_secureRamFuncs_runstart) nonSecureRamFuncs : LOAD = FLASH_ABCDEFGH, PAGE = 0 /* Used by file Flash.c */ RUN = L4SARAM, PAGE = 1 /* Load to flash, run from nonsecure RAM */ LOAD_START(_nonsecureRamFuncs_loadstart), LOAD_SIZE(_nonsecureRamFuncs_loadsize), RUN_START(_nonsecureRamFuncs_runstart) } /******************end of file******************************/
