Problem with memory allocation in InstaSpin Lab

GEOFF JACKSON

Other Parts Discussed in Thread: MOTORWARE

I've added quite a few lines of additional code to an already modified version of Lab13b and now I'm getting error messages when I try to build. Initially I fixed the problem by modifying this line

RAML0_L7 : origin = 0x008000, length = 0x00B800 /* on-chip RAM block RAML0-L6 (was 0x00A0000, increased to B800) */

in the f28069M_ram_lnk.cmd file, to allocate more ram but then ran out of ram again as I added more code. Now I've selected the Flash build configuration to try to run most of the code from flash, but I still get the following messages

>> Compilation failure

program will not fit into available memory. placement with

alignment/blocking fails for section ".text" size 0x9404 page 0. Available

memory ranges:

FLASHA_B size: 0x7f80 unused: 0x7a1f max hole: 0x7a1e

"C:/ti/motorware/motorware_1_01_00_12_jwcamera/sw/ide/ccs/cmd/f2806x/F28069M.cmd", line 136: error #10099-D:

program will not fit into available memory. run placement with

alignment/blocking fails for section ".ebss" size 0x6dbe page 1. Available

memory ranges:

RAML2_3 size: 0x1400 unused: 0x1400 max hole: 0x1400

error #10010: errors encountered during linking; "proj_lab13b_test.out" not

built

gmake: *** [proj_lab13b_test.out] Error 1

gmake: Target `all' not remade because of errors.

I'm pretty lost as to what I need to do to make this work, and don't really understand what the whole memory allocation process is about.

What does selecting a Flash build configuration actually do, as I understood that all of the memory allocation configuration occurs in the ...lnk.cmd file ?

I'm really looking for someone to give me the exact steps I need to take to get the configuration into a state where I can get most of the code into flash and just leave time-critical code, like interrupt routines, in ram. Some indication of where to read up on how the memory allocation works would be good too.

Thanks,

Geoff

over 12 years ago

0 Nicholas Oborny over 12 years ago

TI__Mastermind 21320 points

Hi Geoff,

I am going to move this over to the InstaSPIN forum. They will better be able to assist you.

0 Lori Heustess over 12 years ago

TI__Guru* 93800 points

Hi Geoff,

Could you post the linker .cmd file with your modifications?

GEOFF JACKSON said:
I'm pretty lost as to what I need to do to make this work, and don't really understand what the whole memory allocation process is about.

There is a wiki article that speaks a bit about the linking process and memory allocation. It may help to clarify what the goal is.

http://processors.wiki.ti.com/index.php/C28x_Compiler_-_Understanding_Linking

The .ebss allocation issue may be due to the data page blocking mentioned in that wiki article.

GEOFF JACKSON said:
What does selecting a Flash build configuration actually do, as I understood that all of the memory allocation configuration occurs in the ...lnk.cmd file ?

In Code Composer Studio a user can define a number of different build configurations and they are defined however the user likes:

They can be named anything "Flash" or "MyTest".
They can each have different compiler options. For example a build configuration called "Release" may turn on the optimizer to a high level on specific files or all files.
They can also each include / exclude files. For example a "Flash" configuration may include the linker .cmd file that has flash defined, while the "RAM" build configuration includes a different linker command file.

GEOFF JACKSON said:
I'm really looking for someone to give me the exact steps I need to take to get the configuration into a state where I can get most of the code into flash and just leave time-critical code, like interrupt routines, in ram. Some indication of where to read up on how the memory allocation works would be good too.

This application note is a really good one for describing how to allocate to flash and move time critical code to RAM.

http://www.ti.com/lit/spra958.pdf

0 GEOFF JACKSON over 12 years ago in reply to Lori Heustess

Expert 1535 points

Hi Lori,

Thanks for your very detailed reply.

I'm in the UK and it's quite late here now, so I'll have a look at the documents you recommended tomorrow.

At least I can see now that the configurations use different .cmd files to specify ram or flash. Presumably the F28069M.cmd file is the one used for a flash configuration ?

In the meantime, here's the linker .cmd file that I modified. It's just the one line that I changed. Had to change the extension to .txt as it wouldn't allow me to attache a .cmd file.

RAML0_L7 : origin = 0x008000, length = 0x00B800 /* on-chip RAM block RAML0-L6 (was 0x00A0000, increased to B800) */

Regards,

Geoff

Fullscreen 1205.f28069M_ram_lnk.txt Download

/*
// TI File $Revision: /main/3 $
// Checkin $Date: March 3, 2011   13:45:43 $
//###########################################################################
//
// FILE:    28069_RAM_lnk.cmd
//
// TITLE:   Linker Command File For F28069 examples that run out of RAM
//
//          This ONLY includes all SARAM blocks on the F28069 device.
//          This does not include flash or OTP.
//
//          Keep in mind that L0,L1,L2,L3 and L4 are protected by the code
//          security module.
//
//          What this means is in most cases you will want to move to
//          another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: 2806x C/C++ Header Files V1.10 $ 
// $Release Date: April 7, 2011 $ 
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\F2806x_headers\cmd
//
// For BIOS applications add:      F2806x_Headers_BIOS.cmd
// For nonBIOS applications add:   F2806x_Headers_nonBIOS.cmd
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l F2806x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l F2806x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\F2806x_headers\cmd to the
   library search path under project->build options, linker tab,
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F2806x
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes:
         Memory blocks on F28069 are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.

         Contiguous SARAM memory blocks can be combined
         if required to create a larger memory block.
*/

MEMORY
{
PAGE 0 :

   BEGIN       : origin = 0x000000, length = 0x000002    /* BEGIN is used for the "boot to SARAM" bootloader mode   */
   RAMM0       : origin = 0x000050, length = 0x0003B0
   RAML0_L7    : origin = 0x008000, length = 0x00B800	 /* on-chip RAM block RAML0-L6 (was 0x00A0000, increased to B800) */

   RESET       : origin = 0x3FFFC0, length = 0x000002
   FPUTABLES   : origin = 0x3FD590, length = 0x0006A0	 /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FDC30, length = 0x000B50    /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FE780, length = 0x00008C    /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FE80C, length = 0x0000AA	 /* IQ Math Tables in Boot ROM */

   BOOTROM    : origin = 0x3FF3B0, length = 0x000C10


PAGE 1 :

   BOOT_RSVD   : origin = 0x000002, length = 0x00004E    /* Part of M0, BOOT rom will use this for stack */
   RAMM1       : origin = 0x000400, length = 0x000400    /* on-chip RAM block M1 */
   USB_RAM     : origin = 0x040000, length = 0x000800    /* USB RAM */
}


SECTIONS
{
   /* Setup for "boot to SARAM" mode:
      The codestart section (found in DSP28_CodeStartBranch.asm)
      re-directs execution to the start of user code.  */
   codestart        : > BEGIN,      PAGE = 0
   ramfuncs         : > RAMM0,
                        LOAD_START(_RamfuncsLoadStart),
                        LOAD_END(_RamfuncsLoadEnd),
                        RUN_START(_RamfuncsRunStart),
                        LOAD_SIZE(_RamfuncsLoadSize),
                                    PAGE = 0
   .text            : > RAML0_L7,   PAGE = 0
   .cinit           : > RAMM0,      PAGE = 0
   .pinit           : > RAMM0,      PAGE = 0
   .switch          : > RAMM0,      PAGE = 0
   .reset           : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */

   .stack           : > RAMM1,      PAGE = 1
   .ebss            : > RAML0_L7,   PAGE = 0
   .econst          : > RAML0_L7,   PAGE = 0
   .esysmem         : > RAML0_L7,   PAGE = 0

   IQmath           : > RAML0_L7,   PAGE = 0
   IQmathTables     : > IQTABLES,   PAGE = 0, TYPE = NOLOAD
   
   /* Allocate FPU math areas: */
   FPUmathTables    : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
   
   /* DMARAML4_6	        : > RAML4_6,      PAGE = 1  /* */


  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
#ifdef POSITION // IQNexp tables required for position projects
   IQmathTables2	: > IQTABLES2,			PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
#endif

   /* Uncomment the section below if calling the IQNasin() or IQasin()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

   }
   */

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

0 GEOFF JACKSON over 12 years ago in reply to Lori Heustess

Expert 1535 points

Hi Lori,

Sorry, but the linker command file I attached last night was incorrect. I've tried again this morning, using the following steps.

1. I modified the F28069m.cmd file to use FLASHC in addition to FLASHA_B with the following line

.text : > FLASHA_B|FLASHC, PAGE = 0

2. Tried to build the code and got the following error message

program will not fit into available memory. placement with
alignment/blocking fails for section ".text" size 0x9400 page 0. Available
memory ranges:
FLASHA_B size: 0x7f80 unused: 0x7a24 max hole: 0x7a24
FLASHC size: 0x4000 unused: 0x4000 max hole: 0x4000
error #10010: errors encountered during linking; "proj_lab13b_test.out" not
built

The map file shows flash usage as

name origin length used unused attr fill

FLASHH 003d8000 00004000 00000000 00004000 RWIX
FLASHG 003dc000 00004000 00000000 00004000 RWIX
FLASHF 003e0000 00004000 00000000 00004000 RWIX
FLASHE 003e4000 00004000 00000000 00004000 RWIX
FLASHD 003e8000 00004000 00000341 00003cbf RWIX
FLASHC 003ec000 00004000 00000000 00004000 RWIX
FLASHA_B 003f0000 00007f80 0000055c 00007a24 RWIX

It seems to me that the .text code size is 0x9400, but the map file says that only 0x55C of FLASHA_B has been used.

Clearly I'm getting something wrong here, but I've no idea what.

I'm attaching the .cmd and .map files. Please let me know if you need anything else.

Geoff3833.proj_lab13b_test_map.txt

Fullscreen 8561.F28069M_cmd.txt Download

/*
//###########################################################################
//
// FILE:    F28069.cmd
//
// TITLE:   Linker Command File For F28069 Device
//
//###########################################################################
// $TI Release: F2806x C/C++ Header Files and Peripheral Examples V135 $ 
// $Release Date: Sep 8, 2012 $ 
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\F2806x_headers\cmd
//
// For BIOS applications add:      F2806x_Headers_BIOS.cmd
// For nonBIOS applications add:   F2806x_Headers_nonBIOS.cmd
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l F2806x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l F2806x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\F2806x_headers\cmd to the
   library search path under project->build options, linker tab,
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F2806x
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes:
         Memory blocks on F28069 are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.

         Contiguous SARAM memory blocks can be combined
         if required to create a larger memory block.
*/

MEMORY
{
PAGE 0 :   /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
   RAML0       : origin = 0x008000, length = 0x000800     /* on-chip RAM block L0 */
   RAML1       : origin = 0x008800, length = 0x000400     /* on-chip RAM block L1 */
   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */

   FLASHH      : origin = 0x3D8000, length = 0x004000     /* on-chip FLASH */
   FLASHG      : origin = 0x3DC000, length = 0x004000     /* on-chip FLASH */
   FLASHF      : origin = 0x3E0000, length = 0x004000     /* on-chip FLASH */
   FLASHE      : origin = 0x3E4000, length = 0x004000     /* on-chip FLASH */   
   FLASHD      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
   FLASHC      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
   FLASHA_B    : origin = 0x3F0000, length = 0x007F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   FPUTABLES   : origin = 0x3FD590, length = 0x0006A0	 /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FDC30, length = 0x000B50    /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FE780, length = 0x00008C    /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FE80C, length = 0x0000AA	 /* IQ Math Tables in Boot ROM */

   ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML2_3     : origin = 0x008C00, length = 0x001400     /* on-chip RAM block L2 */
   RAML4       : origin = 0x00A000, length = 0x002000     /* on-chip RAM block L4 */
   RAML5       : origin = 0x00C000, length = 0x002000     /* on-chip RAM block L5 */
   RAML6       : origin = 0x00E000, length = 0x002000     /* on-chip RAM block L6 */
   RAML7       : origin = 0x010000, length = 0x002000     /* on-chip RAM block L7 */
   RAML8       : origin = 0x012000, length = 0x001800     /* on-chip RAM block L8 */
   USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */   
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/


SECTIONS
{

   /* Allocate program areas: */
   .cinit              : > FLASHA_B,   PAGE = 0
   .pinit              : > FLASHA_B,   PAGE = 0
   .text               : > FLASHA_B|FLASHC,   PAGE = 0
   codestart           : > BEGIN,      PAGE = 0
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         PAGE = 0

   csmpasswds          : > CSM_PWL_P0, PAGE = 0
   csm_rsvd            : > CSM_RSVD,   PAGE = 0

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0,      PAGE = 1
   .ebss               : > RAML2_3,    PAGE = 1
   .esysmem            : > RAML2_3,    PAGE = 1

   /* Initalized sections to go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA_B,   PAGE = 0
   .switch             : > FLASHA_B,   PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : > FLASHA_B,   PAGE = 0            /* Math Code */
   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD
   
   /* Allocate FPU math areas: */
   FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
   
   DMARAML5	           : > RAML5,      PAGE = 1
   DMARAML6	           : > RAML6,      PAGE = 1
   DMARAML7	           : > RAML7,      PAGE = 1
   DMARAML8	           : > RAML8,      PAGE = 1   

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
#ifdef POSITION // IQNexp tables required for position projects
   IQmathTables2	: > IQTABLES2,			PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
#endif

   /* Uncomment the section below if calling the IQNasin() or IQasin()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

   }
   */

   /* .reset is a standard section used by the compiler.  It contains the */
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS,    PAGE = 0, TYPE = DSECT

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

0 Adam D. Reynolds over 12 years ago in reply to GEOFF JACKSON

Guru 12800 points

Geoff,

It looks like I told you something slightly incorrect. When you want to split a section over multiple memory ranges the syntax is slightly different. You need to add a second > to the line. See the example below.

.text             : >> FLASHA_B | FLASHC,     PAGE = 0

Please give this a shot.

0 GEOFF JACKSON over 12 years ago in reply to Adam D. Reynolds

Expert 1535 points

Thanks Adam,

Only just had chance to look at this, but that was it.

Where is this kind of subtle difference documented ?

Geoff

0 Adam D. Reynolds over 12 years ago in reply to GEOFF JACKSON

Guru 12800 points

I found the answer here: http://processors.wiki.ti.com/index.php/C28x_Compiler_-_Understanding_Linking#Q:_The_linker_says_.22placement_fails_for_object_.27.text.27_.22._How_can_I_make_more_memory_available_for_.text.3F

0 Lori Heustess over 12 years ago in reply to GEOFF JACKSON

TI__Guru* 93800 points

GEOFF JACKSON said:

Thanks Adam,

Only just had chance to look at this, but that was it.

Where is this kind of subtle difference documented ?

Geoff

Geoff,

In addition to the Wiki article Adam mentioned, the linker is documented in www.ti.com/lit/spru513

happy coding!

Lori

C2000™︎ microcontrollers

C2000 microcontrollers forum

Problem with memory allocation in InstaSpin Lab