28069 Running from FLASH

Shane Rock

Other Parts Discussed in Thread: CONTROLSUITE

I have an application that runs fine from RAM but when I attempt to run it from FLASH nothing seems to work none of my variables work and timer0 is not even working. I've followed the example in the controlSuite and that worked fine, but for whatever reason I can't get my own code to work.

Below is my code

#include "project.h"

#define DISPLAY
//MOTOR Global Variables
float desiredSpeed=0, actualSpeed=0, deltaSpeed=0.04, startSpeed=5;
float lowSpeed=65, highSpeed=240;
int  state=0, timer=0,ms=0,mm=0,ss=0, counter_30=0;



//###############################################################
//						Main Application
//###############################################################
void main(void)
{
	InitSysCtrl();
	myInitGpio();				// Initialize GPIO for speaker, display, and motor
	DINT;
	InitPieCtrl();
	IER = 0x0000;
	IFR = 0x0000;
	InitPieVectTable();
	EALLOW;  				// This is needed to write to EALLOW protected registers
	PieVectTable.TINT0 = &cpu_timer0_isr;
	PieVectTable.TINT1 = &cpu_timer1_isr;
	EDIS;    				// This is needed to disable write to EALLOW protected registers
	InitCpuTimers();   			// Initialize the Cpu Timers
#ifdef FLASH					// Put application into FLASH
	memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (Uint32)&RamfuncsRunStart);
	InitFlash();	// Call the flash wrapper init function
#endif
	ConfigCpuTimer(&CpuTimer0, 90, 1000);
	ConfigCpuTimer(&CpuTimer1, 90, 1000);
	CpuTimer0Regs.TCR.all = 0x4000; 	// Start CPU timer
	MOTORDISABLE;				// Ensure motor is off

	// User specific code, enable interrupts:
	IER |= M_INT1;  			// TINT0
	IER |= M_INT13; 			// TINT1

	PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
	EINT;   				// Enable Global interrupt INTM
	ERTM;   				// Enable Global realtime interrupt DBGM
	delayms(1000);
	MOTORFORWARD; MOTORM0HI; MOTORM1HI; MOTORM2HI;		// Set motor direction and 1/32 microstepping
	delayms(200);
	clrRST; delayms(200); setRST; delayms(200); 	// reset display and put into known state
	displayInit();					// Initialize Display
	showwords(0x0000);
	while (1)
	{
		switch (state)
		{
			case 0:
				showtxt(1,"   BARD PERIPHERAL  ",0);
				showtxt(2,"      VASCULAR      ",0);
				delayms(1000);
				state=1;

			case 1:
				showtxt(1,"   SETUP REQUIRED   ",0);
				showtxt(2,"                    ",0);
				if (actualSpeed==0) { MOTORDISABLE; STOPTIMER1; }
				if (FLUSH_PB)
				{
					actualSpeed=startSpeed;
					ConfigCpuTimer(&CpuTimer1,90,PERIOD(actualSpeed));
					desiredSpeed=highSpeed;
					MOTORENABLE;
					delayms(20);
					STARTTIMER1;
					state=2;
				}
				break;
			case 2:
				if (!FLUSH_PB)
				{
					delayms(2000);
					desiredSpeed=0;
					state=3;
				}
				break;
			case 3:
				if (actualSpeed==0) { MOTORDISABLE; STOPTIMER1; }
				showtxt(1,"   SYSTEM READY     ",0);
				showtxt(2,"        TIME:       ",0);
				showtime(8,10,mm,ss,0);
				state=4;
				break;
			case 4:
				if (actualSpeed==0) { MOTORDISABLE; STOPTIMER1; }
				if (HANDPIECE_PB)
				{
					actualSpeed=startSpeed;
					ConfigCpuTimer(&CpuTimer1,90,PERIOD(actualSpeed));
					desiredSpeed=lowSpeed;
					MOTORENABLE;
					delayms(20);
					STARTTIMER1;
					delayms(1000);		// Make sure button is released before moving to next state
					state=5;
				}
				break;
			case 5:
				if (HANDPIECE_PB)
					state=7;
				else
				{
					delayms(3000);
					timer=1;
					counter_30=0;
					state=6;
				}
				break;
			case 6:
				if (HANDPIECE_PB)
					state=7;
				showtxt(1,"     ENERGY ON      ",0);
				showtime(8,10,mm,ss,0);
				if(counter_30>29&&mm<5)
					state=7;
				if(mm==5)
					state=8;
				break;
			case 7:
				desiredSpeed=0;
				timer=0;
				state=3;
				delayms(1000);			// Make sure button is released before moving to next state
				break;
			case 8:
				desiredSpeed=0;
				timer=0;
				delayms(1000);
				showtxt(1,"   TIME EXPIRED     ",0);
				showtxt(2,"   CHANGE DEVICE    ",0);
				if (actualSpeed==0) { MOTORDISABLE; STOPTIMER1; }
		}

	}
}
//##################################################################
//						End Main Application
//##################################################################


//##################################################################
//						CPU Timer0 (used for delayms function)
//##################################################################
__interrupt void cpu_timer0_isr(void)
{
	CpuTimer0.InterruptCount++;
	//if (T0val>0) T0val--;

	if(timer)
	{
		ms++;
		if(ms>999)
		{
			ss++;
			counter_30++;
			ms=0;
			if(ss>59)
			{
				mm++;
				ss=0;
			}
		}
	}
        PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
//##################################################################
//						End CPU Timer0 (used for delayms function)
//##################################################################


//##################################################################
//						CPU Timer1 (used to set speed of motor)
//##################################################################
__interrupt void cpu_timer1_isr(void)
{
	volatile Uint32 ii=0;
   CpuTimer1.InterruptCount++;
   if (desiredSpeed>actualSpeed) {
	   actualSpeed+=deltaSpeed;
	   if (actualSpeed>desiredSpeed) actualSpeed=desiredSpeed;
   }
   if (desiredSpeed<actualSpeed) {
	   actualSpeed-=deltaSpeed;
	   if (actualSpeed<desiredSpeed) actualSpeed=desiredSpeed;
   }
   if (actualSpeed>0) {
	   MOTORSTEPHI; for (ii=0;ii<35;ii++); MOTORSTEPLO;
   }
   if(actualSpeed != desiredSpeed)
   {
	   ConfigCpuTimer(&CpuTimer1,90,PERIOD(actualSpeed));
	   STARTTIMER1;
   }
   EDIS;
}
//####################################################################
//						End CPU Timer1 (used to set speed of motor)
//####################################################################


//###################################################################
//						Delay milliseconds
//###################################################################
void delayms(int t)
{
	CpuTimer0.InterruptCount=0;
	while (CpuTimer0.InterruptCount<t);
}
//###################################################################
//						End Delay milliseconds
//###################################################################

#ifdef DISPLAY
//####################################################################
//						Display Initialization
//####################################################################
void displayInit()
{
	sendboth(0x00, 0x0001 ); delayms(10); // start osc
	sendboth(0x01, 0x0000 ); delayms(10); // driver control
	sendboth(0x03, 0x0030 ); delayms(10); // power control(1)
	sendboth(0x04, 0x0701 ); delayms(10); // power control (2)
	sendboth(0x05, kont );   delayms(10); // contrast
	sendboth(0x23, 0x0004 ); delayms(10); // mono
	sendboth(0x20, 0xFF00 ); delayms(10); // display mode control
	sendboth(0x28, 0x000C ); delayms(10); // frame control
	sendboth(0x29, 0x0015 ); delayms(10); //
	sendboth(0x37, 0x0200 ); delayms(10); //
	sendboth(0x07, 0x0001 ); delayms(10); // display control
	sendboth(0x02, 0x0145 ); delayms(10); //
	sendboth(0x0D, 0x4F00 ); delayms(10); // RAM window horizontal
	sendboth(0x0E, 0xEF00 ); delayms(10); // RAM window vertical
	sendboth(0x08, 0x0000 ); delayms(10); // RAM address
	sendboth(0x06, 0x0003 ); delayms(10); // entry mode
}
//####################################################################
//						End Display Initialization
//####################################################################


//####################################################################
//						Show Image
//						Display a 320x240 image in black and white (1 bit per pixel)
//####################################################################
void showimg(cuint x[])
{
	int ii;
	sendboth(0x01, 0x0010 ); delayms(10); // driver control
	sendboth(0x06, 0x0003 ); delayms(10); // entry mode
	sendboth(0x08, 0x0000 ); delayms(1);
	send(0x09,0);
	for (ii=0;ii<240*20;ii++) send(x[ii],1);
}
//#################################################################
//						End Show Image
//#################################################################


//#################################################################
//						Show Words
//						Display 16 bits repeatedly all over display
//						0x0000=black 0xFFFF=white 0xAAAA=narrow stripes 0xFF00=wide stripes
//#################################################################
void showwords(ushort v)
{
	uint ii,max=9600; 					//320*240/8=40*240
	sendboth(0x06, 0x0003 ); delayms(10); 			// entry mode
	sendboth(0x08, 0x0000 ); delayms(1);
	send(0x09,0);
	for (ii=0;ii<max;ii++)
	{
		send(v,1);
	}

}
//#################################################################
//						End Show Words
//#################################################################


//################################################################
//						Show Text
// 						Display one line of text font size 24 at row position y
// 						msg must be 20 characters,
// 						inv=0 white chars on black bkgnd, inv=1 inverted
//################################################################
void showtxt(float y, char msg[],uchar inv)
{
	static int pos,row,col,chidx,sidx,tbidx;
	static ushort v;
	static uchar line[28][40];
	for (row=0; row<consola24H; row++) {
		for (col=0; col<40; col++) {
			line[row][col]=0xF0;
		}
	}
	for (pos=0;pos<20;pos++) {
		chidx=msg[pos]-32;
		tbidx= (int)consola24B * (int)consola24H * chidx;
		for (row=0; row<consola24H; row++) {
			for (col=0; col<consola24B; col++) {
				sidx=tbidx+consola24B*row+col;
				if (inv) v=0xFF^consola24[sidx]; else v=consola24[sidx];
				line[row][2*pos+col]= v;
			}
		}

	}
	sendboth(0x01, 0x0000 ); delayms(10); // driver control
	sendboth(0x06, 0x0003 ); delayms(10); // entry mode
	pos=((int)(.5+y * (float)(consola24H-2)))<<8;
	sendboth(0x08, pos ); delayms(1);
	send(0x09,0);
	for (col=0; col<40; col+=2) {
		v=(line[0][col]<<8)|(line[0][col+1]);
		send(v,1);
	}
	for (row=0; row<consola24H-3; row++) {
		for (col=0; col<40; col+=2) {
			v=(line[row][col]<<8)|(line[row][col+1]);
			send(v,1);
		}
	}
}
//###############################################################
//						End Show Text
//###############################################################


//###############################################################
//						Show Time
// 						Display time mm:ss at row position y, 16-bit column position x
// 						using font size 58, normal or inverted
//###############################################################
void showtime(int x, float y, int mins, int secs, uchar inv)
{
	char msg[6],bkgnd;
	int pos,row,col,chidx,sidx,tbidx;
	ushort v;
	uchar line[68][40];
	if (inv) bkgnd=0xFF; else bkgnd=0x00;
	for (row=0; row<consola58H; row++) {
		for (col=0; col<40; col++) {
			line[row][col]=bkgnd;
		}
	}
	msg[0]=mins/10; msg[1]=mins%10;	msg[2]=10; msg[3]=secs/10; msg[4]=secs%10;
	for (pos=0;pos<5;pos++) {
		chidx=msg[pos];
		if (chidx==0 && pos==0) continue;
		tbidx= (int)consola58B * (int)consola58H * chidx;
		for (row=0; row<consola58H; row++) {
			for (col=0; col<consola58B; col++) {
				sidx=tbidx+consola58B*row+col;
				if (inv) v=0xFF^consola58[sidx]; else v=consola58[sidx];
				line[row][consola58B*pos+col+x]= v;
			}
		}

	}
	sendboth(0x01, 0x0000 ); delayms(10); // driver control
	sendboth(0x06, 0x0003 ); delayms(10); // entry mode
	pos=((int)(.5+y * (float)(consola58H-2)))<<8;
	sendboth(0x08, pos ); delayms(1);
	send(0x09,0);
	for (col=0; col<40; col+=2) {
		v=(line[0][col]<<8)|(line[0][col+1]);
		send(v,1);
	}
	for (row=0; row<consola58H-3; row++) {
		for (col=0; col<40; col+=2) {
			v=(line[row][col]<<8)|(line[row][col+1]);
			send(v,1);
		}
	}
}
//################################################################
//						End Show Time
//################################################################


//################################################################
//						Send - to display
// 						Send (bit bang) 16-bit data v, MSB first,
// 						rs=0 address, rs=1 data
//################################################################
void send(ushort v, uchar rs)
{
	volatile int ii,xx=0;
	clrCSB;
	if (rs==1) setRS; else clrRS;
	for (ii=0;ii<16;ii++) {
		clrSCL;
		if ((v & 0x8000)==0) clrSDA; else setSDA;
		setSCL;
		v<<=1;
	}
	setSDA; setCSB;
}
//###########################################################
//						End Send
//###########################################################


//###########################################################
//						Send both (address then data)
//###########################################################
void sendboth(ushort idx, ushort val)
{
	send(idx,0); send(val,1);
}
//##########################################################
//						End Send both
//##########################################################
#endif

Below is my linker file: (note: I had to increase the size of .ebss)

/*
//###########################################################################
//
// FILE:    F28069.cmd
//
// TITLE:   Linker Command File For F28069 Device
//
//###########################################################################
// $TI Release: F2806x C/C++ Header Files and Peripheral Examples V136 $ 
// $Release Date: Apr 15, 2013 $ 
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\F2806x_headers\cmd
//
// For BIOS applications add:      F2806x_Headers_BIOS.cmd
// For nonBIOS applications add:   F2806x_Headers_nonBIOS.cmd
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l F2806x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l F2806x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\F2806x_headers\cmd to the
   library search path under project->build options, linker tab,
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F2806x
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes:
         Memory blocks on F28069 are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.

         Contiguous SARAM memory blocks can be combined
         if required to create a larger memory block.
*/

MEMORY
{
PAGE 0 :   /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
   RAML0       : origin = 0x008000, length = 0x000800     /* on-chip RAM block L0 */
   RAML1       : origin = 0x008800, length = 0x000400     /* on-chip RAM block L1 */
   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */

   FLASHH      : origin = 0x3D8000, length = 0x004000     /* on-chip FLASH */
   FLASHG      : origin = 0x3DC000, length = 0x004000     /* on-chip FLASH */
   FLASHF      : origin = 0x3E0000, length = 0x004000     /* on-chip FLASH */
   FLASHE      : origin = 0x3E4000, length = 0x004000     /* on-chip FLASH */   
   FLASHD      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
   FLASHC      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
   FLASHA      : origin = 0x3F4000, length = 0x003F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   FPUTABLES   : origin = 0x3FD860, length = 0x0006A0	  /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FDF00, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEA50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FEADC, length = 0x0000AA	  /* IQ Math Tables in Boot ROM */

   ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML2_3       : origin = 0x008C00, length = 0x001400     /* on-chip RAM block L2 */
   //RAML3       : origin = 0x009000, length = 0x001000	  /* on-chip RAM block L3 */
   RAML4       : origin = 0x00A000, length = 0x002000     /* on-chip RAM block L4 */
   RAML5       : origin = 0x00C000, length = 0x002000     /* on-chip RAM block L5 */
   RAML6       : origin = 0x00E000, length = 0x002000     /* on-chip RAM block L6 */
   RAML7       : origin = 0x010000, length = 0x002000     /* on-chip RAM block L7 */
   RAML8       : origin = 0x012000, length = 0x002000     /* on-chip RAM block L8 */
   USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */   
   FLASHB      : origin = 0x3F0000, length = 0x004000     /* on-chip FLASH */     
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/


SECTIONS
{

   /* Allocate program areas: */
   .cinit              : > FLASHA,     PAGE = 0
   .pinit              : > FLASHA,     PAGE = 0
   .text               : > FLASHA,     PAGE = 0
   codestart           : > BEGIN,      PAGE = 0
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
						 LOAD_SIZE(_RamfuncsLoadSize),
                         PAGE = 0

   csmpasswds          : > CSM_PWL_P0, PAGE = 0
   csm_rsvd            : > CSM_RSVD,   PAGE = 0

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0,      PAGE = 1
   .ebss               : > RAML2_3,      PAGE = 1
   .esysmem            : > RAML2_3,      PAGE = 1

   /* Initalized sections to go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA,     PAGE = 0
   .switch             : > FLASHA,     PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : > FLASHA,     PAGE = 0            /* Math Code */
   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD
   
   /* Allocate FPU math areas: */
   FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
   
   DMARAML5	           : > RAML5,      PAGE = 1
   DMARAML6	           : > RAML6,      PAGE = 1
   DMARAML7	           : > RAML7,      PAGE = 1
   DMARAML8	           : > RAML8,      PAGE = 1   

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
    /* Uncomment the section below if calling the IQNasin() or IQasin()
       functions from the IQMath.lib library in order to utilize the
       relevant IQ Math table in Boot ROM (This saves space and Boot ROM
       is 1 wait-state). If this section is not uncommented, IQmathTables2
       will be loaded into other memory (SARAM, Flash, etc.) and will take
       up space, but 0 wait-state is possible.
    */
    /*
    IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
    {

               IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

    }
    */

   /* .reset is a standard section used by the compiler.  It contains the */
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS,    PAGE = 0, TYPE = DSECT

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Below is my map file:

******************************************************************************
             TMS320C2000 Linker PC v6.1.0                      
******************************************************************************
>> Linked Wed Oct 15 15:55:29 2014

OUTPUT FILE NAME:   <UIIO_CrosserComplete_Rev_XA.out>
ENTRY POINT SYMBOL: "_c_int00"  address: 003f6ef5


MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
PAGE 0:
  RAML0                 00008000   00000800  0000001f  000007e1  RWIX
  RAML1                 00008800   00000400  00000000  00000400  RWIX
  OTP                   003d7800   00000400  00000000  00000400  RWIX
  FLASHH                003d8000   00004000  00000000  00004000  RWIX
  FLASHG                003dc000   00004000  00000000  00004000  RWIX
  FLASHF                003e0000   00004000  00000000  00004000  RWIX
  FLASHE                003e4000   00004000  00000000  00004000  RWIX
  FLASHD                003e8000   00004000  0000001f  00003fe1  RWIX
  FLASHC                003ec000   00004000  00000000  00004000  RWIX
  FLASHA                003f4000   00003f80  00003080  00000f00  RWIX
  CSM_RSVD              003f7f80   00000076  00000000  00000076  RWIX
  BEGIN                 003f7ff6   00000002  00000002  00000000  RWIX
  CSM_PWL_P0            003f7ff8   00000008  00000000  00000008  RWIX
  FPUTABLES             003fd860   000006a0  00000000  000006a0  RWIX
  IQTABLES              003fdf00   00000b50  00000000  00000b50  RWIX
  IQTABLES2             003fea50   0000008c  00000000  0000008c  RWIX
  IQTABLES3             003feadc   000000aa  00000000  000000aa  RWIX
  ROM                   003ff3b0   00000c10  00000000  00000c10  RWIX
  RESET                 003fffc0   00000002  00000000  00000002  RWIX
  VECTORS               003fffc2   0000003e  00000000  0000003e  RWIX

PAGE 1:
  BOOT_RSVD             00000000   00000050  00000000  00000050  RWIX
  RAMM0                 00000050   000003b0  00000300  000000b0  RWIX
  RAMM1                 00000400   00000400  00000000  00000400  RWIX
  DEV_EMU               00000880   00000105  00000004  00000101  RWIX
  SYS_PWR_CTL           00000985   00000003  00000003  00000000  RWIX
  FLASH_REGS            00000a80   00000060  00000008  00000058  RWIX
  CSM                   00000ae0   00000020  00000010  00000010  RWIX
  ADC_RESULT            00000b00   00000020  00000010  00000010  RWIX
  CPU_TIMER0            00000c00   00000008  00000008  00000000  RWIX
  CPU_TIMER1            00000c08   00000008  00000008  00000000  RWIX
  CPU_TIMER2            00000c10   00000008  00000008  00000000  RWIX
  PIE_CTRL              00000ce0   00000020  0000001a  00000006  RWIX
  PIE_VECT              00000d00   00000100  00000100  00000000  RWIX
  DMA                   00001000   00000200  000000e0  00000120  RWIX
  CLA1                  00001400   00000080  00000040  00000040  RWIX
  USB0                  00004000   00001000  00000454  00000bac  RWIX
  McBSPA                00005000   00000040  00000024  0000001c  RWIX
  ECANA                 00006000   00000040  00000034  0000000c  RWIX
  ECANA_LAM             00006040   00000040  00000040  00000000  RWIX
  ECANA_MOTS            00006080   00000040  00000040  00000000  RWIX
  ECANA_MOTO            000060c0   00000040  00000040  00000000  RWIX
  ECANA_MBOX            00006100   00000100  00000100  00000000  RWIX
  COMP1                 00006400   00000020  00000014  0000000c  RWIX
  COMP2                 00006420   00000020  00000014  0000000c  RWIX
  COMP3                 00006440   00000020  00000014  0000000c  RWIX
  EPWM1                 00006800   00000040  00000040  00000000  RWIX
  EPWM2                 00006840   00000040  00000040  00000000  RWIX
  EPWM3                 00006880   00000040  00000040  00000000  RWIX
  EPWM4                 000068c0   00000040  00000040  00000000  RWIX
  EPWM5                 00006900   00000040  00000040  00000000  RWIX
  EPWM6                 00006940   00000040  00000040  00000000  RWIX
  EPWM7                 00006980   00000040  00000040  00000000  RWIX
  EPWM8                 000069c0   00000040  00000040  00000000  RWIX
  ECAP1                 00006a00   00000020  00000020  00000000  RWIX
  ECAP2                 00006a20   00000020  00000020  00000000  RWIX
  ECAP3                 00006a40   00000020  00000020  00000000  RWIX
  HRCAP1                00006ac0   00000020  00000020  00000000  RWIX
  HRCAP2                00006ae0   00000020  00000020  00000000  RWIX
  EQEP1                 00006b00   00000040  00000022  0000001e  RWIX
  EQEP2                 00006b40   00000040  00000022  0000001e  RWIX
  HRCAP3                00006c80   00000020  00000020  00000000  RWIX
  HRCAP4                00006ca0   00000020  00000020  00000000  RWIX
  GPIOCTRL              00006f80   00000040  00000040  00000000  RWIX
  GPIODAT               00006fc0   00000020  00000020  00000000  RWIX
  GPIOINT               00006fe0   00000020  00000020  00000000  RWIX
  SYSTEM                00007010   00000030  00000030  00000000  RWIX
  SPIA                  00007040   00000010  00000010  00000000  RWIX
  SCIA                  00007050   00000010  00000010  00000000  RWIX
  NMIINTRUPT            00007060   00000010  00000010  00000000  RWIX
  XINTRUPT              00007070   00000010  00000010  00000000  RWIX
  ADC                   00007100   00000080  00000050  00000030  RWIX
  SPIB                  00007740   00000010  00000010  00000000  RWIX
  SCIB                  00007750   00000010  00000010  00000000  RWIX
  I2CA                  00007900   00000040  00000022  0000001e  RWIX
  RAML2_3               00008c00   00001400  000004c0  00000f40  RWIX
  RAML4                 0000a000   00002000  00000000  00002000  RWIX
  RAML5                 0000c000   00002000  00000000  00002000  RWIX
  RAML6                 0000e000   00002000  00000000  00002000  RWIX
  RAML7                 00010000   00002000  00000000  00002000  RWIX
  RAML8                 00012000   00002000  00000000  00002000  RWIX
  USB_RAM               00040000   00000800  00000000  00000800  RWIX
  PARTID                003d7e80   00000001  00000001  00000000  RWIX
  FLASHB                003f0000   00004000  00000000  00004000  RWIX
  CSM_PWL               003f7ff8   00000008  00000008  00000000  RWIX


SECTION ALLOCATION MAP

 output                                  attributes/
section   page    origin      length       input sections
--------  ----  ----------  ----------   ----------------
.pinit     0    003f4000    00000000     UNINITIALIZED

ramfuncs   0    003e8000    0000001f     RUN ADDR = 00008000
                  003e8000    0000001b     F2806x_SysCtrl.obj (ramfuncs)
                  003e801b    00000004     F2806x_usDelay.obj (ramfuncs)

.econst    0    003f4000    00002245     
                  003f4000    000014c8     main.obj (.econst:_consola24)
                  003f54c8    00000bb0     main.obj (.econst:_consola58)
                  003f6078    00000100     F2806x_PieVect.obj (.econst)
                  003f6178    000000c5     main.obj (.econst:.string)
                  003f623d    00000008     main.obj (.econst)

.text      0    003f6245    00000de3     
                  003f6245    00000558     main.obj (.text)
                  003f679d    0000039b     F2806x_DefaultIsr.obj (.text:retain)
                  003f6b38    0000017f     F2806x_SysCtrl.obj (.text)
                  003f6cb7    000000dc     main.obj (.text:retain)
                  003f6d93    00000088     rts2800_fpu32.lib : fs_div.obj (.text)
                  003f6e1b    00000073     F2806x_CpuTimers.obj (.text)
                  003f6e8e    00000067     peripheral_setup.obj (.text)
                  003f6ef5    00000046     rts2800_fpu32.lib : boot.obj (.text)
                  003f6f3b    00000028     F2806x_PieCtrl.obj (.text)
                  003f6f63    00000025     F2806x_PieVect.obj (.text)
                  003f6f88    00000022     rts2800_fpu32.lib : i_div.obj (.text)
                  003f6faa    00000021                       : memcpy_ff.obj (.text)
                  003f6fcb    0000001a     F2806x_Gpio.obj (.text)
                  003f6fe5    00000019     rts2800_fpu32.lib : args_main.obj (.text)
                  003f6ffe    00000019                       : exit.obj (.text)
                  003f7017    00000009                       : _lock.obj (.text)
                  003f7020    00000008     F2806x_CodeStartBranch.obj (.text)

.cinit     0    003f7028    00000058     
                  003f7028    00000042     main.obj (.cinit)
                  003f706a    0000000a     rts2800_fpu32.lib : _lock.obj (.cinit)
                  003f7074    0000000a                       : exit.obj (.cinit)
                  003f707e    00000002     --HOLE-- [fill = 0]

codestart 
*          0    003f7ff6    00000002     
                  003f7ff6    00000002     F2806x_CodeStartBranch.obj (codestart)

.reset     0    003fffc0    00000002     DSECT
                  003fffc0    00000002     rts2800_fpu32.lib : boot.obj (.reset)

vectors    0    003fffc2    00000000     DSECT

.stack     1    00000050    00000300     UNINITIALIZED
                  00000050    00000300     --HOLE--

DevEmuRegsFile 
*          1    00000880    00000004     UNINITIALIZED
                  00000880    00000004     F2806x_GlobalVariableDefs.obj (DevEmuRegsFile)

SysPwrCtrlRegsFile 
*          1    00000985    00000003     UNINITIALIZED
                  00000985    00000003     F2806x_GlobalVariableDefs.obj (SysPwrCtrlRegsFile)

FlashRegsFile 
*          1    00000a80    00000008     UNINITIALIZED
                  00000a80    00000008     F2806x_GlobalVariableDefs.obj (FlashRegsFile)

CsmRegsFile 
*          1    00000ae0    00000010     UNINITIALIZED
                  00000ae0    00000010     F2806x_GlobalVariableDefs.obj (CsmRegsFile)

AdcResultFile 
*          1    00000b00    00000010     UNINITIALIZED
                  00000b00    00000010     F2806x_GlobalVariableDefs.obj (AdcResultFile)

CpuTimer0RegsFile 
*          1    00000c00    00000008     UNINITIALIZED
                  00000c00    00000008     F2806x_GlobalVariableDefs.obj (CpuTimer0RegsFile)

CpuTimer1RegsFile 
*          1    00000c08    00000008     UNINITIALIZED
                  00000c08    00000008     F2806x_GlobalVariableDefs.obj (CpuTimer1RegsFile)

CpuTimer2RegsFile 
*          1    00000c10    00000008     UNINITIALIZED
                  00000c10    00000008     F2806x_GlobalVariableDefs.obj (CpuTimer2RegsFile)

PieCtrlRegsFile 
*          1    00000ce0    0000001a     UNINITIALIZED
                  00000ce0    0000001a     F2806x_GlobalVariableDefs.obj (PieCtrlRegsFile)

PieVectTableFile 
*          1    00000d00    00000100     UNINITIALIZED
                  00000d00    00000100     F2806x_GlobalVariableDefs.obj (PieVectTableFile)

EmuKeyVar 
*          1    00000d00    00000001     UNINITIALIZED
                  00000d00    00000001     F2806x_GlobalVariableDefs.obj (EmuKeyVar)

EmuBModeVar 
*          1    00000d01    00000001     UNINITIALIZED
                  00000d01    00000001     F2806x_GlobalVariableDefs.obj (EmuBModeVar)

FlashCallbackVar 
*          1    00000d02    00000002     UNINITIALIZED
                  00000d02    00000002     F2806x_GlobalVariableDefs.obj (FlashCallbackVar)

FlashScalingVar 
*          1    00000d04    00000002     UNINITIALIZED
                  00000d04    00000002     F2806x_GlobalVariableDefs.obj (FlashScalingVar)

DmaRegsFile 
*          1    00001000    000000e0     UNINITIALIZED
                  00001000    000000e0     F2806x_GlobalVariableDefs.obj (DmaRegsFile)

Cla1RegsFile 
*          1    00001400    00000040     UNINITIALIZED
                  00001400    00000040     F2806x_GlobalVariableDefs.obj (Cla1RegsFile)

Usb0RegsFile 
*          1    00004000    00000454     UNINITIALIZED
                  00004000    00000454     F2806x_GlobalVariableDefs.obj (Usb0RegsFile)

McbspaRegsFile 
*          1    00005000    00000024     UNINITIALIZED
                  00005000    00000024     F2806x_GlobalVariableDefs.obj (McbspaRegsFile)

ECanaRegsFile 
*          1    00006000    00000034     UNINITIALIZED
                  00006000    00000034     F2806x_GlobalVariableDefs.obj (ECanaRegsFile)

ECanaLAMRegsFile 
*          1    00006040    00000040     UNINITIALIZED
                  00006040    00000040     F2806x_GlobalVariableDefs.obj (ECanaLAMRegsFile)

ECanaMOTSRegsFile 
*          1    00006080    00000040     UNINITIALIZED
                  00006080    00000040     F2806x_GlobalVariableDefs.obj (ECanaMOTSRegsFile)

ECanaMOTORegsFile 
*          1    000060c0    00000040     UNINITIALIZED
                  000060c0    00000040     F2806x_GlobalVariableDefs.obj (ECanaMOTORegsFile)

ECanaMboxesFile 
*          1    00006100    00000100     UNINITIALIZED
                  00006100    00000100     F2806x_GlobalVariableDefs.obj (ECanaMboxesFile)

Comp1RegsFile 
*          1    00006400    00000014     UNINITIALIZED
                  00006400    00000014     F2806x_GlobalVariableDefs.obj (Comp1RegsFile)

Comp2RegsFile 
*          1    00006420    00000014     UNINITIALIZED
                  00006420    00000014     F2806x_GlobalVariableDefs.obj (Comp2RegsFile)

Comp3RegsFile 
*          1    00006440    00000014     UNINITIALIZED
                  00006440    00000014     F2806x_GlobalVariableDefs.obj (Comp3RegsFile)

EPwm1RegsFile 
*          1    00006800    00000040     UNINITIALIZED
                  00006800    00000040     F2806x_GlobalVariableDefs.obj (EPwm1RegsFile)

EPwm2RegsFile 
*          1    00006840    00000040     UNINITIALIZED
                  00006840    00000040     F2806x_GlobalVariableDefs.obj (EPwm2RegsFile)

EPwm3RegsFile 
*          1    00006880    00000040     UNINITIALIZED
                  00006880    00000040     F2806x_GlobalVariableDefs.obj (EPwm3RegsFile)

EPwm4RegsFile 
*          1    000068c0    00000040     UNINITIALIZED
                  000068c0    00000040     F2806x_GlobalVariableDefs.obj (EPwm4RegsFile)

EPwm5RegsFile 
*          1    00006900    00000040     UNINITIALIZED
                  00006900    00000040     F2806x_GlobalVariableDefs.obj (EPwm5RegsFile)

EPwm6RegsFile 
*          1    00006940    00000040     UNINITIALIZED
                  00006940    00000040     F2806x_GlobalVariableDefs.obj (EPwm6RegsFile)

EPwm7RegsFile 
*          1    00006980    00000040     UNINITIALIZED
                  00006980    00000040     F2806x_GlobalVariableDefs.obj (EPwm7RegsFile)

EPwm8RegsFile 
*          1    000069c0    00000040     UNINITIALIZED
                  000069c0    00000040     F2806x_GlobalVariableDefs.obj (EPwm8RegsFile)

ECap1RegsFile 
*          1    00006a00    00000020     UNINITIALIZED
                  00006a00    00000020     F2806x_GlobalVariableDefs.obj (ECap1RegsFile)

ECap2RegsFile 
*          1    00006a20    00000020     UNINITIALIZED
                  00006a20    00000020     F2806x_GlobalVariableDefs.obj (ECap2RegsFile)

ECap3RegsFile 
*          1    00006a40    00000020     UNINITIALIZED
                  00006a40    00000020     F2806x_GlobalVariableDefs.obj (ECap3RegsFile)

HRCap1RegsFile 
*          1    00006ac0    00000020     UNINITIALIZED
                  00006ac0    00000020     F2806x_GlobalVariableDefs.obj (HRCap1RegsFile)

HRCap2RegsFile 
*          1    00006ae0    00000020     UNINITIALIZED
                  00006ae0    00000020     F2806x_GlobalVariableDefs.obj (HRCap2RegsFile)

EQep1RegsFile 
*          1    00006b00    00000022     UNINITIALIZED
                  00006b00    00000022     F2806x_GlobalVariableDefs.obj (EQep1RegsFile)

EQep2RegsFile 
*          1    00006b40    00000022     UNINITIALIZED
                  00006b40    00000022     F2806x_GlobalVariableDefs.obj (EQep2RegsFile)

HRCap3RegsFile 
*          1    00006c80    00000020     UNINITIALIZED
                  00006c80    00000020     F2806x_GlobalVariableDefs.obj (HRCap3RegsFile)

HRCap4RegsFile 
*          1    00006ca0    00000020     UNINITIALIZED
                  00006ca0    00000020     F2806x_GlobalVariableDefs.obj (HRCap4RegsFile)

GpioCtrlRegsFile 
*          1    00006f80    00000040     UNINITIALIZED
                  00006f80    00000040     F2806x_GlobalVariableDefs.obj (GpioCtrlRegsFile)

GpioDataRegsFile 
*          1    00006fc0    00000020     UNINITIALIZED
                  00006fc0    00000020     F2806x_GlobalVariableDefs.obj (GpioDataRegsFile)

GpioIntRegsFile 
*          1    00006fe0    00000020     UNINITIALIZED
                  00006fe0    00000020     F2806x_GlobalVariableDefs.obj (GpioIntRegsFile)

SysCtrlRegsFile 
*          1    00007010    00000030     UNINITIALIZED
                  00007010    00000030     F2806x_GlobalVariableDefs.obj (SysCtrlRegsFile)

SpiaRegsFile 
*          1    00007040    00000010     UNINITIALIZED
                  00007040    00000010     F2806x_GlobalVariableDefs.obj (SpiaRegsFile)

SciaRegsFile 
*          1    00007050    00000010     UNINITIALIZED
                  00007050    00000010     F2806x_GlobalVariableDefs.obj (SciaRegsFile)

NmiIntruptRegsFile 
*          1    00007060    00000010     UNINITIALIZED
                  00007060    00000010     F2806x_GlobalVariableDefs.obj (NmiIntruptRegsFile)

XIntruptRegsFile 
*          1    00007070    00000010     UNINITIALIZED
                  00007070    00000010     F2806x_GlobalVariableDefs.obj (XIntruptRegsFile)

AdcRegsFile 
*          1    00007100    00000050     UNINITIALIZED
                  00007100    00000050     F2806x_GlobalVariableDefs.obj (AdcRegsFile)

SpibRegsFile 
*          1    00007740    00000010     UNINITIALIZED
                  00007740    00000010     F2806x_GlobalVariableDefs.obj (SpibRegsFile)

ScibRegsFile 
*          1    00007750    00000010     UNINITIALIZED
                  00007750    00000010     F2806x_GlobalVariableDefs.obj (ScibRegsFile)

I2caRegsFile 
*          1    00007900    00000022     UNINITIALIZED
                  00007900    00000022     F2806x_GlobalVariableDefs.obj (I2caRegsFile)

.ebss      1    00008c00    000004c0     UNINITIALIZED
                  00008c00    000004a0     main.obj (.ebss)
                  000090a0    00000018     F2806x_CpuTimers.obj (.ebss)
                  000090b8    00000004     rts2800_fpu32.lib : _lock.obj (.ebss)
                  000090bc    00000004                       : exit.obj (.ebss)

PartIdRegsFile 
*          1    003d7e80    00000001     UNINITIALIZED
                  003d7e80    00000001     F2806x_GlobalVariableDefs.obj (PartIdRegsFile)

CsmPwlFile 
*          1    003f7ff8    00000008     UNINITIALIZED
                  003f7ff8    00000008     F2806x_GlobalVariableDefs.obj (CsmPwlFile)


GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name 

address    name
--------   ----
003f6245   .text
003f6ffe   C$$EXIT
003f6d93   FS$$DIV
003f6f88   I$$DIV
003f6f99   I$$MOD
003f685b   _ADCINT1_ISR
003f6865   _ADCINT2_ISR
003f6a6d   _ADCINT3_ISR
003f6a77   _ADCINT4_ISR
003f6a81   _ADCINT5_ISR
003f6a8b   _ADCINT6_ISR
003f6a95   _ADCINT7_ISR
003f6a9f   _ADCINT8_ISR
003f6883   _ADCINT9_ISR
00007100   _AdcRegs
00000b00   _AdcResult
003f6aa9   _CLA1_INT1_ISR
003f6ab3   _CLA1_INT2_ISR
003f6abd   _CLA1_INT3_ISR
003f6ac7   _CLA1_INT4_ISR
003f6ad1   _CLA1_INT5_ISR
003f6adb   _CLA1_INT6_ISR
003f6ae5   _CLA1_INT7_ISR
003f6aef   _CLA1_INT8_ISR
00001400   _Cla1Regs
00006400   _Comp1Regs
00006420   _Comp2Regs
00006440   _Comp3Regs
003f6e54   _ConfigCpuTimer
000090b0   _CpuTimer0
00000c00   _CpuTimer0Regs
000090a0   _CpuTimer1
00000c08   _CpuTimer1Regs
000090a8   _CpuTimer2
00000c10   _CpuTimer2Regs
003f7ff8   _CsmPwl
00000ae0   _CsmRegs
003f6c38   _CsmUnlock
003f67b1   _DATALOG_ISR
003f69e1   _DINTCH1_ISR
003f69eb   _DINTCH2_ISR
003f69f5   _DINTCH3_ISR
003f69ff   _DINTCH4_ISR
003f6a09   _DINTCH5_ISR
003f6a13   _DINTCH6_ISR
0000801b   _DSP28x_usDelay
00000880   _DevEmuRegs
003f6b5c   _DisableDog
00001000   _DmaRegs
003f6a59   _ECAN0INTA_ISR
003f6a63   _ECAN1INTA_ISR
003f6941   _ECAP1_INT_ISR
003f694b   _ECAP2_INT_ISR
003f6955   _ECAP3_INT_ISR
00006040   _ECanaLAMRegs
000060c0   _ECanaMOTORegs
00006080   _ECanaMOTSRegs
00006100   _ECanaMboxes
00006000   _ECanaRegs
00006a00   _ECap1Regs
00006a20   _ECap2Regs
00006a40   _ECap3Regs
003f6b17   _EMPTY_ISR
003f67c5   _EMUINT_ISR
003f68f1   _EPWM1_INT_ISR
003f68a1   _EPWM1_TZINT_ISR
003f68fb   _EPWM2_INT_ISR
003f68ab   _EPWM2_TZINT_ISR
003f6905   _EPWM3_INT_ISR
003f68b5   _EPWM3_TZINT_ISR
003f690f   _EPWM4_INT_ISR
003f68bf   _EPWM4_TZINT_ISR
003f6919   _EPWM5_INT_ISR
003f68c9   _EPWM5_TZINT_ISR
003f6923   _EPWM6_INT_ISR
003f68d3   _EPWM6_TZINT_ISR
003f692d   _EPWM7_INT_ISR
003f68dd   _EPWM7_TZINT_ISR
003f6937   _EPWM8_INT_ISR
003f68e7   _EPWM8_TZINT_ISR
00006800   _EPwm1Regs
00006840   _EPwm2Regs
00006880   _EPwm3Regs
000068c0   _EPwm4Regs
00006900   _EPwm5Regs
00006940   _EPwm6Regs
00006980   _EPwm7Regs
000069c0   _EPwm8Regs
003f6973   _EQEP1_INT_ISR
003f697d   _EQEP2_INT_ISR
00006b00   _EQep1Regs
00006b40   _EQep2Regs
00000d01   _EmuBMode
00000d00   _EmuKey
003f6f5a   _EnableInterrupts
003f6ca1   _ExtOscSel
00000a80   _FlashRegs
00000d04   _Flash_CPUScaleFactor
00000d02   _Flash_CallbackPtr
00006f80   _GpioCtrlRegs
00006fc0   _GpioDataRegs
00006fe0   _GpioIntRegs
003f695f   _HRCAP1_INT_ISR
003f6969   _HRCAP2_INT_ISR
003f6987   _HRCAP3_INT_ISR
003f6991   _HRCAP4_INT_ISR
00006ac0   _HRCap1Regs
00006ae0   _HRCap2Regs
00006c80   _HRCap3Regs
00006ca0   _HRCap4Regs
003f6a1d   _I2CINT1A_ISR
003f6a27   _I2CINT2A_ISR
00007900   _I2caRegs
003f67d9   _ILLEGAL_ISR
003f679d   _INT13_ISR
003f67a7   _INT14_ISR
003f6e1b   _InitCpuTimers
00008000   _InitFlash
003f6fcb   _InitGpio
003f6be2   _InitPeripheralClocks
003f6f3b   _InitPieCtrl
003f6f63   _InitPieVectTable
003f6b64   _InitPll
003f6bb4   _InitPll2
003f6b38   _InitSysCtrl
003f6c69   _IntOsc1Sel
003f6c79   _IntOsc2Sel
003f6b0d   _LUF_ISR
003f6b03   _LVF_ISR
003f69cd   _MRINTA_ISR
003f69d7   _MXINTA_ISR
00005000   _McbspaRegs
003f67cf   _NMI_ISR
00007060   _NmiIntruptRegs
003f6b24   _PIE_RESERVED
003d7e80   _PartIdRegs
00000ce0   _PieCtrlRegs
00000d00   _PieVectTable
003f6078   _PieVectTableInit
003f67bb   _RTOSINT_ISR
003e801f   _RamfuncsLoadEnd
0000001f   _RamfuncsLoadSize
003e8000   _RamfuncsLoadStart
00008000   _RamfuncsRunStart
003f6a31   _SCIRXINTA_ISR
003f6a45   _SCIRXINTB_ISR
003f6a3b   _SCITXINTA_ISR
003f6a4f   _SCITXINTB_ISR
003f69a5   _SPIRXINTA_ISR
003f69b9   _SPIRXINTB_ISR
003f69af   _SPITXINTA_ISR
003f69c3   _SPITXINTB_ISR
00007050   _SciaRegs
00007750   _ScibRegs
003f6b52   _ServiceDog
00007040   _SpiaRegs
00007740   _SpibRegs
00007010   _SysCtrlRegs
00000985   _SysPwrCtrlRegs
003f688d   _TINT0_ISR
003f699b   _USB0_INT_ISR
003f683d   _USER10_ISR
003f6847   _USER11_ISR
003f6851   _USER12_ISR
003f67e3   _USER1_ISR
003f67ed   _USER2_ISR
003f67f7   _USER3_ISR
003f6801   _USER4_ISR
003f680b   _USER5_ISR
003f6815   _USER6_ISR
003f681f   _USER7_ISR
003f6829   _USER8_ISR
003f6833   _USER9_ISR
00004000   _Usb0Regs
003f6897   _WAKEINT_ISR
003f686f   _XINT1_ISR
003f6879   _XINT2_ISR
003f6af9   _XINT3_ISR
00007070   _XIntruptRegs
003f6c8d   _XtalOscSel
00000350   __STACK_END
00000300   __STACK_SIZE
00000001   __TI_args_main
ffffffff   ___binit__
ffffffff   ___c_args__
003f7028   ___cinit__
003f7028   ___etext__
003f6faa   ___memcpy_ff
ffffffff   ___pinit__
003f6245   ___text__
003f6fe5   __args_main
000090bc   __cleanup_ptr
000090be   __dtors_ptr
000090ba   __lock
003f701f   __nop
003f701b   __register_lock
003f7017   __register_unlock
00000050   __stack
000090b8   __unlock
003f6ffe   _abort
00008c12   _actualSpeed
003f6ef5   _c_int00
003f4000   _consola24
003f6243   _consola24B
003f6242   _consola24H
003f623e   _consola24L
003f6244   _consola24W
003f54c8   _consola58
003f6240   _consola58B
003f6241   _consola58H
003f623d   _consola58L
003f623f   _consola58W
00008c0a   _counter_30
003f6cb7   _cpu_timer0_isr
003f6ce5   _cpu_timer1_isr
003f6456   _delayms
00008c14   _deltaSpeed
00008c1a   _desiredSpeed
003f6462   _displayInit
003f7000   _exit
003f6788   _handpiece_pressed
00008c16   _highSpeed
00008c0e   _kont
00008c18   _lowSpeed
003f6245   _main
00008c03   _mm
00008c01   _ms
003f6e8e   _myInitGpio
00008c0d   _pressed_debounce
00008c0c   _released_debounce
003f6b2e   _rsvd_ISR
003f6751   _send
003f677c   _sendboth
003f64db   _showimg
003f6637   _showtime
003f652d   _showtxt
003f6509   _showwords
00008c0b   _ss
00008c1c   _startSpeed
00008c00   _state
00008c02   _timer
ffffffff   binit
003f7028   cinit
003f7ff6   code_start
003f7028   etext
ffffffff   pinit


GLOBAL SYMBOLS: SORTED BY Symbol Address 

address    name
--------   ----
00000001   __TI_args_main
0000001f   _RamfuncsLoadSize
00000050   __stack
00000300   __STACK_SIZE
00000350   __STACK_END
00000880   _DevEmuRegs
00000985   _SysPwrCtrlRegs
00000a80   _FlashRegs
00000ae0   _CsmRegs
00000b00   _AdcResult
00000c00   _CpuTimer0Regs
00000c08   _CpuTimer1Regs
00000c10   _CpuTimer2Regs
00000ce0   _PieCtrlRegs
00000d00   _EmuKey
00000d00   _PieVectTable
00000d01   _EmuBMode
00000d02   _Flash_CallbackPtr
00000d04   _Flash_CPUScaleFactor
00001000   _DmaRegs
00001400   _Cla1Regs
00004000   _Usb0Regs
00005000   _McbspaRegs
00006000   _ECanaRegs
00006040   _ECanaLAMRegs
00006080   _ECanaMOTSRegs
000060c0   _ECanaMOTORegs
00006100   _ECanaMboxes
00006400   _Comp1Regs
00006420   _Comp2Regs
00006440   _Comp3Regs
00006800   _EPwm1Regs
00006840   _EPwm2Regs
00006880   _EPwm3Regs
000068c0   _EPwm4Regs
00006900   _EPwm5Regs
00006940   _EPwm6Regs
00006980   _EPwm7Regs
000069c0   _EPwm8Regs
00006a00   _ECap1Regs
00006a20   _ECap2Regs
00006a40   _ECap3Regs
00006ac0   _HRCap1Regs
00006ae0   _HRCap2Regs
00006b00   _EQep1Regs
00006b40   _EQep2Regs
00006c80   _HRCap3Regs
00006ca0   _HRCap4Regs
00006f80   _GpioCtrlRegs
00006fc0   _GpioDataRegs
00006fe0   _GpioIntRegs
00007010   _SysCtrlRegs
00007040   _SpiaRegs
00007050   _SciaRegs
00007060   _NmiIntruptRegs
00007070   _XIntruptRegs
00007100   _AdcRegs
00007740   _SpibRegs
00007750   _ScibRegs
00007900   _I2caRegs
00008000   _InitFlash
00008000   _RamfuncsRunStart
0000801b   _DSP28x_usDelay
00008c00   _state
00008c01   _ms
00008c02   _timer
00008c03   _mm
00008c0a   _counter_30
00008c0b   _ss
00008c0c   _released_debounce
00008c0d   _pressed_debounce
00008c0e   _kont
00008c12   _actualSpeed
00008c14   _deltaSpeed
00008c16   _highSpeed
00008c18   _lowSpeed
00008c1a   _desiredSpeed
00008c1c   _startSpeed
000090a0   _CpuTimer1
000090a8   _CpuTimer2
000090b0   _CpuTimer0
000090b8   __unlock
000090ba   __lock
000090bc   __cleanup_ptr
000090be   __dtors_ptr
003d7e80   _PartIdRegs
003e8000   _RamfuncsLoadStart
003e801f   _RamfuncsLoadEnd
003f4000   _consola24
003f54c8   _consola58
003f6078   _PieVectTableInit
003f623d   _consola58L
003f623e   _consola24L
003f623f   _consola58W
003f6240   _consola58B
003f6241   _consola58H
003f6242   _consola24H
003f6243   _consola24B
003f6244   _consola24W
003f6245   .text
003f6245   ___text__
003f6245   _main
003f6456   _delayms
003f6462   _displayInit
003f64db   _showimg
003f6509   _showwords
003f652d   _showtxt
003f6637   _showtime
003f6751   _send
003f677c   _sendboth
003f6788   _handpiece_pressed
003f679d   _INT13_ISR
003f67a7   _INT14_ISR
003f67b1   _DATALOG_ISR
003f67bb   _RTOSINT_ISR
003f67c5   _EMUINT_ISR
003f67cf   _NMI_ISR
003f67d9   _ILLEGAL_ISR
003f67e3   _USER1_ISR
003f67ed   _USER2_ISR
003f67f7   _USER3_ISR
003f6801   _USER4_ISR
003f680b   _USER5_ISR
003f6815   _USER6_ISR
003f681f   _USER7_ISR
003f6829   _USER8_ISR
003f6833   _USER9_ISR
003f683d   _USER10_ISR
003f6847   _USER11_ISR
003f6851   _USER12_ISR
003f685b   _ADCINT1_ISR
003f6865   _ADCINT2_ISR
003f686f   _XINT1_ISR
003f6879   _XINT2_ISR
003f6883   _ADCINT9_ISR
003f688d   _TINT0_ISR
003f6897   _WAKEINT_ISR
003f68a1   _EPWM1_TZINT_ISR
003f68ab   _EPWM2_TZINT_ISR
003f68b5   _EPWM3_TZINT_ISR
003f68bf   _EPWM4_TZINT_ISR
003f68c9   _EPWM5_TZINT_ISR
003f68d3   _EPWM6_TZINT_ISR
003f68dd   _EPWM7_TZINT_ISR
003f68e7   _EPWM8_TZINT_ISR
003f68f1   _EPWM1_INT_ISR
003f68fb   _EPWM2_INT_ISR
003f6905   _EPWM3_INT_ISR
003f690f   _EPWM4_INT_ISR
003f6919   _EPWM5_INT_ISR
003f6923   _EPWM6_INT_ISR
003f692d   _EPWM7_INT_ISR
003f6937   _EPWM8_INT_ISR
003f6941   _ECAP1_INT_ISR
003f694b   _ECAP2_INT_ISR
003f6955   _ECAP3_INT_ISR
003f695f   _HRCAP1_INT_ISR
003f6969   _HRCAP2_INT_ISR
003f6973   _EQEP1_INT_ISR
003f697d   _EQEP2_INT_ISR
003f6987   _HRCAP3_INT_ISR
003f6991   _HRCAP4_INT_ISR
003f699b   _USB0_INT_ISR
003f69a5   _SPIRXINTA_ISR
003f69af   _SPITXINTA_ISR
003f69b9   _SPIRXINTB_ISR
003f69c3   _SPITXINTB_ISR
003f69cd   _MRINTA_ISR
003f69d7   _MXINTA_ISR
003f69e1   _DINTCH1_ISR
003f69eb   _DINTCH2_ISR
003f69f5   _DINTCH3_ISR
003f69ff   _DINTCH4_ISR
003f6a09   _DINTCH5_ISR
003f6a13   _DINTCH6_ISR
003f6a1d   _I2CINT1A_ISR
003f6a27   _I2CINT2A_ISR
003f6a31   _SCIRXINTA_ISR
003f6a3b   _SCITXINTA_ISR
003f6a45   _SCIRXINTB_ISR
003f6a4f   _SCITXINTB_ISR
003f6a59   _ECAN0INTA_ISR
003f6a63   _ECAN1INTA_ISR
003f6a6d   _ADCINT3_ISR
003f6a77   _ADCINT4_ISR
003f6a81   _ADCINT5_ISR
003f6a8b   _ADCINT6_ISR
003f6a95   _ADCINT7_ISR
003f6a9f   _ADCINT8_ISR
003f6aa9   _CLA1_INT1_ISR
003f6ab3   _CLA1_INT2_ISR
003f6abd   _CLA1_INT3_ISR
003f6ac7   _CLA1_INT4_ISR
003f6ad1   _CLA1_INT5_ISR
003f6adb   _CLA1_INT6_ISR
003f6ae5   _CLA1_INT7_ISR
003f6aef   _CLA1_INT8_ISR
003f6af9   _XINT3_ISR
003f6b03   _LVF_ISR
003f6b0d   _LUF_ISR
003f6b17   _EMPTY_ISR
003f6b24   _PIE_RESERVED
003f6b2e   _rsvd_ISR
003f6b38   _InitSysCtrl
003f6b52   _ServiceDog
003f6b5c   _DisableDog
003f6b64   _InitPll
003f6bb4   _InitPll2
003f6be2   _InitPeripheralClocks
003f6c38   _CsmUnlock
003f6c69   _IntOsc1Sel
003f6c79   _IntOsc2Sel
003f6c8d   _XtalOscSel
003f6ca1   _ExtOscSel
003f6cb7   _cpu_timer0_isr
003f6ce5   _cpu_timer1_isr
003f6d93   FS$$DIV
003f6e1b   _InitCpuTimers
003f6e54   _ConfigCpuTimer
003f6e8e   _myInitGpio
003f6ef5   _c_int00
003f6f3b   _InitPieCtrl
003f6f5a   _EnableInterrupts
003f6f63   _InitPieVectTable
003f6f88   I$$DIV
003f6f99   I$$MOD
003f6faa   ___memcpy_ff
003f6fcb   _InitGpio
003f6fe5   __args_main
003f6ffe   C$$EXIT
003f6ffe   _abort
003f7000   _exit
003f7017   __register_unlock
003f701b   __register_lock
003f701f   __nop
003f7028   ___cinit__
003f7028   ___etext__
003f7028   cinit
003f7028   etext
003f7ff6   code_start
003f7ff8   _CsmPwl
ffffffff   ___binit__
ffffffff   ___c_args__
ffffffff   ___pinit__
ffffffff   binit
ffffffff   pinit

[246 symbols]

over 11 years ago

0 Shane Rock over 11 years ago

Intellectual 450 points

I changed my memcpy command from

"memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (Uint32)&RamfuncsRunStart);"

"memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (Uint32)&RamfuncsLoadSize);"

and this allows the program to at least run part way but when I click the button and it goes from state = 2 to state = 3 the variables start going hay wire.

any ideas?

0 Manoj Santha Mohan over 11 years ago in reply to Shane Rock

TI__Guru 55700 points

Shane,

These are some of the comman mistakes people make when they run standlone from flash. Hope this checklist helps you resolve the problem.

source: http://processors.wiki.ti.com/index.php/C2000_Flash_Common_Issues/FAQs

Running Code Standalone

Q: How do I need to change my code for it to run stand-alone (without CCS connected)?

A: Refer to these resources:

Running an Application from Flash (spra958)
Copying Compiler Sections from Flash to RAM on the TMS320F28xxx DSCs (spraau8)
In the documentation for the C28x Header Files and Peripheral Examples includes a section that describes how to migrate RAM based project to a flash based project.
The C28x Header Files and Peripheral Examples include a simple flash based example.

Code Does Not Run Standalone

Q: My program runs correctly when debugging within CCS but when I attempt to run this standalone it does not work. Why is this occurring?

A: This can occur for a few different reasons:

The boot mode selection is not "jump to flash". Check the boot ROM guide and data manual for the particular device.
There are initialized sections allocated to load to RAM instead of flash. All initialized sections should have their load addresses allocated to flash so they can be programmed. The .cmd file needs to be checked to ensure that all initialized sections are assigned to flash. Section 3 of the Running an Application from Internal Flash Memory on the TMS320F28xx DSP(SPRA958) App. Note explains where each compiler generated section should be allocated.
If the code is time critical and needs to be run from RAM, it can be copied at runtime.
After you copy critical sections to RAM, make sure the copy really occurred - check the memory contents.
Try running the flash to RAM copy routine first. Some early functions may assume parts have been copied to RAM. For example, the delay function is used in the InitSysCtrl() function. This delay function is by default allocated to the functions TI's examples copy to RAM. If InitSysCtrl() is called before the copy to RAM then an exception will occur. TI is working to add comments to help avoid this pitfall. This also occurs with InitAdc().
An instruction was not added to branch to the beginning of application code at the flash entry point. This is discussed further in Section 6 of SPRA958.
281x specific: In addition to the actual boot pins, the MP/MC pin needs to be pulled low to enable the boot ROM.

To debug this issue, step through the code and try to determine where it is going wrong. Here are some debug suggestions:

Flash the device
Turn off the power
Connect CCS and select "load symbols" only
Place a breakpoint at the entry point to flash
Reset the part with the debugger and run - did you hit the breakpoint? If so the boot mode looks ok
Step the code until you find an issue.

Regards,

Manoj

0 Shane Rock over 11 years ago in reply to Manoj Santha Mohan

Intellectual 450 points

so I found a different linker file that was found that was from a different project and it is working fine now but I really can't seem to figure out why the default one would not work, maybe someone here could explain it to me?

Default linker (doesn't work)

MEMORY
{
PAGE 0:		/* Program Memory */
           	/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
   RAML0       : origin = 0x008000, length = 0x000800     /* on-chip RAM block L0 */
   RAML1       : origin = 0x008800, length = 0x000400     /* on-chip RAM block L1 */
   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */

   FLASHH      : origin = 0x3D8000, length = 0x004000     /* on-chip FLASH */
   FLASHG      : origin = 0x3DC000, length = 0x004000     /* on-chip FLASH */
   FLASHF      : origin = 0x3E0000, length = 0x004000     /* on-chip FLASH */
   FLASHE      : origin = 0x3E4000, length = 0x004000     /* on-chip FLASH */   
   FLASHD      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
   FLASHC      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
   FLASHA      : origin = 0x3F4000, length = 0x003F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   FPUTABLES   : origin = 0x3FD860, length = 0x0006A0	  /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FDF00, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEA50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FEADC, length = 0x0000AA	  /* IQ Math Tables in Boot ROM */

   ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML2_3       : origin = 0x008C00, length = 0x001400     /* on-chip RAM block L2 */
   //RAML3       : origin = 0x009000, length = 0x001000	  /* on-chip RAM block L3 */
   RAML4       : origin = 0x00A000, length = 0x002000     /* on-chip RAM block L4 */
   RAML5       : origin = 0x00C000, length = 0x002000     /* on-chip RAM block L5 */
   RAML6       : origin = 0x00E000, length = 0x002000     /* on-chip RAM block L6 */
   RAML7       : origin = 0x010000, length = 0x002000     /* on-chip RAM block L7 */
   RAML8       : origin = 0x012000, length = 0x002000     /* on-chip RAM block L8 */
   USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */   
   FLASHB      : origin = 0x3F0000, length = 0x004000     /* on-chip FLASH */     
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/


SECTIONS
{

   /* Allocate program areas: */
   .cinit              : > FLASHA,     PAGE = 0
   .pinit              : > FLASHA,     PAGE = 0
   .text               : > FLASHA,     PAGE = 0
   codestart           : > BEGIN,      PAGE = 0
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
						 LOAD_SIZE(_RamfuncsLoadSize),
                         PAGE = 0

   csmpasswds          : > CSM_PWL_P0, PAGE = 0
   csm_rsvd            : > CSM_RSVD,   PAGE = 0

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0,      PAGE = 1
   .ebss               : > RAML2_3,      PAGE = 1
   .esysmem            : > RAML2_3,      PAGE = 1

   /* Initalized sections to go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA,     PAGE = 0
   .switch             : > FLASHA,     PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : > FLASHA,     PAGE = 0            /* Math Code */
   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD
   
   /* Allocate FPU math areas: */
   FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
   
   DMARAML5	           : > RAML5,      PAGE = 1
   DMARAML6	           : > RAML6,      PAGE = 1
   DMARAML7	           : > RAML7,      PAGE = 1
   DMARAML8	           : > RAML8,      PAGE = 1   

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
    /* Uncomment the section below if calling the IQNasin() or IQasin()
       functions from the IQMath.lib library in order to utilize the
       relevant IQ Math table in Boot ROM (This saves space and Boot ROM
       is 1 wait-state). If this section is not uncommented, IQmathTables2
       will be loaded into other memory (SARAM, Flash, etc.) and will take
       up space, but 0 wait-state is possible.
    */
    /*
    IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
    {

               IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

    }
    */

   /* .reset is a standard section used by the compiler.  It contains the */
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS,    PAGE = 0, TYPE = DSECT

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Working linker file

MEMORY
{
PAGE 0:		/* Program Memory */
			/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
	BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
	progRAM		: origin = 0x008000, length = 0x000C00		//on-chip RAM block L0-L1
	OTP         : origin = 0x3D7800, length = 0x000400     	/* on-chip OTP */
	
	FLASHH      : origin = 0x3D8000, length = 0x004000     	/* on-chip FLASH */
   	FLASHG      : origin = 0x3DC000, length = 0x004000     	/* on-chip FLASH */
   	FLASHEF     : origin = 0x3E0000, length = 0x008000     	/* on-chip FLASH */
   	FLASHCD		: origin = 0x3E8000, length = 0x008000
   	FLASHA      : origin = 0x3F4000, length = 0x003F80     	/* on-chip FLASH */
	CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     	/* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
	BEGIN       : origin = 0x3F7FF6, length = 0x000002     	/* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
	CSM_PWL     : origin = 0x3F7FF8, length = 0x000008     	/* Part of FLASHA.  CSM password locations in FLASHA */
	
   	FPUTABLES   : origin = 0x3FD860, length = 0x0006A0	  	/* FPU Tables in Boot ROM */
   	IQTABLES    : origin = 0x3FDF00, length = 0x000B50    	/* IQ Math Tables in Boot ROM */
   	IQTABLES2   : origin = 0x3FEA50, length = 0x00008C    	/* IQ Math Tables in Boot ROM */
   	IQTABLES3   : origin = 0x3FEADC, length = 0x0000AA	  	/* IQ Math Tables in Boot ROM */

	BOOTROM     : origin = 0x3FF3B0, length = 0x000C10     	/* Boot ROM */
	RESET       : origin = 0x3FFFC0, length = 0x000002     	/* part of boot ROM  */
	VECTORS     : origin = 0x3FFFC2, length = 0x00003E     	/* part of boot ROM  */

PAGE 1 : 

	RAMM0       : origin = 0x000050, length = 0x0003B0     	/* on-chip RAM block M0 */
   	RAMM1       : origin = 0x000400, length = 0x000400     	/* on-chip RAM block M1 */
	dataRAM		: origin = 0x008C00, length = 0x001400		// RAML2 and RAML3
   	RAML4       : origin = 0x00A000, length = 0x002000     	/* on-chip RAM block L4 */
   	RAML5       : origin = 0x00C000, length = 0x002000     	/* on-chip RAM block L5 */
   	RAML6       : origin = 0x00E000, length = 0x002000     	/* on-chip RAM block L6 */
   	RAML7       : origin = 0x010000, length = 0x002000     	/* on-chip RAM block L7 */
   	RAML8       : origin = 0x012000, length = 0x002000     	/* on-chip RAM block L8 */
	FLASHB      : origin = 0x3F4000, length = 0x002000
}
 
 
SECTIONS  {
   .cinit              	: > FLASHA,		PAGE = 0
   .pinit              	: > FLASHA,     PAGE = 0
   .text               	: > FLASHCD,    PAGE = 0

   codestart           : > BEGIN       	PAGE = 0
   ramfuncs            : LOAD = FLASHA, 
                         RUN = progRAM, 
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         PAGE = 0

   csmpasswds          	: > CSM_PWL     PAGE = 0
   csm_rsvd            	: > CSM_RSVD    PAGE = 0
   .stack           	: > RAML4,      PAGE = 1
   .ebss            	: > dataRAM,    PAGE = 1
   .esysmem         	: > dataRAM,    PAGE = 1
   .econst             	: > FLASHEF     PAGE = 0
   .switch             	: > FLASHA      PAGE = 0
   IQmath              	: > FLASHA      PAGE = 0                  /* Math Code */
   IQmathTables        	: > IQTABLES    PAGE = 0, TYPE = NOLOAD   /* Math Tables In ROM */
   .reset              	: > RESET,      PAGE = 0, TYPE = DSECT
   vectors             	: > VECTORS     PAGE = 0, TYPE = DSECT
}

SECTIONS  {
	Net_terminals:	> dataRAM,PAGE = 1
}

0 Venugopal S over 10 years ago in reply to Shane Rock

Intellectual 640 points

Hi Shane Rock
Is your problem is resolved?If it is done please help me?
Mine is also same problem.my code is working fine in RAM.but not in flash.I have studied "Running an Application from Internal Flash Memory on the TMS320F28xxx DSP".but i didn't get any thing.please help me.Is there any document for flash programming that will show step by step.

C2000™︎ microcontrollers

C2000 microcontrollers forum

28069 Running from FLASH

source: http://processors.wiki.ti.com/index.php/C2000_Flash_Common_Issues/FAQs

Running Code Standalone

Code Does Not Run Standalone