Hi,
I am having problem with generating negative phase shift for dual active bridge dc-dc converter (consists of two H-bridge--4 converter legs).
The phase shifts between leg1 and 2 of H bridge 1 is D1, leg1 and 2 of H bridge 2 is D2 while D3 controls the power flow direction and magnitude.
If phase shift D3 is positive, the power flows from H-bridge 1 to H-bridge2 while when D3 is negative, power flows in the opposite direction ( from H- bridge 2 to H bridge 1).
The ranges for D1 and D2 are 0 to 180 degress and D3 range -180 degress to 180 degrees.
For positive power flow the Epwm signals respond well and the converter works well. The problem is when D3 is negative and i cannot achive proper phase shift.
This is the code i am running ..
interrupt void adc_isr(void) //this logic is run at the sampling time
{
D1=D11*(9375); //
D2=D22*(9375); //
D3=D33*(9375); //
D23=(D2+D3);//
if (D3>=0)
{
// LEG 2
Setup_ePWM();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
EPwm1Regs.TBCTL.bit.PHSEN = 0;
EPwm1Regs.TBCTL.bit.SYNCOSEL =1; // generate a syncout if CTR = 0
EPwm1Regs.TBPHS.half.TBPHS =0;
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
// LEG 2
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
//
EPwm2Regs.TBCTL.bit.PHSEN = 1; // enable phase shift for ePWM2
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0; // syncin = syncout
// EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm2Regs.TBPHS.half.TBPHS =D1; // PHASE SHIFT=[D1*TS/2]*TBPRD
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
// // LEG 3
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
EPwm3Regs.TBCTL.bit.PHSEN = 1; // enable phase shift for ePWM3
//EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN;
EPwm3Regs.TBCTL.bit.SYNCOSEL = 0; // syncin = syncout
EPwm3Regs.TBPHS.half.TBPHS =D3; //PHASE SHIFT=[D3*TS/2]*TBPRD
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
// // LEG 4
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
EPwm4Regs.TBCTL.bit.PHSEN = 1; // enable phase shift for ePWM4
//EPwm3Regs.TBCTL.bit.PHSDIR = TB_DOWN;//TB_UP;
EPwm4Regs.TBCTL.bit.SYNCOSEL = 0; // syncin = syncout
EPwm4Regs.TBPHS.half.TBPHS =D23; //PHASE SHIFT=[(D2+D3)*TS/2]*TBPRD
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
}
else if (D3<0)
{
D1=D11*9375; //
D2=D22*9375; //
D3=(-1*D33)*9375; //
D23=(D2+D3);//
Setup_ePWM();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
//**********************************ENABLE PHASE SHIFTS FOR LEG 2,LEG 3 & LEG 4 OF THE DAB4*****************************************************************
// // LEG 1 MASTER
EPwm1Regs.TBCTL.bit.PHSEN = 0;
EPwm1Regs.TBCTL.bit.SYNCOSEL = 1; // generate a syncout if CTR = 0
EPwm1Regs.TBPHS.half.TBPHS =0;
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
// // LEG 2
//
//
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
EPwm2Regs.TBCTL.bit.PHSEN = 1; // enable phase shift for ePWM2
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0; // syncin = syncout
EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm2Regs.TBPHS.half.TBPHS =D1; // PHASE SHIFT=[D1*TS/2]*TBPRD
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
// // LEG 3
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
EPwm3Regs.TBCTL.bit.PHSEN = 1; // enable phase shift for ePWM3
EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm3Regs.TBCTL.bit.SYNCOSEL = 0; // syncin = syncout
EPwm3Regs.TBPHS.half.TBPHS =D3; //PHASE SHIFT=[D3*TS/2]*TBPRD
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
// // LEG 4
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
EPwm4Regs.TBCTL.bit.PHSEN = 1; // enable phase shift for ePWM4
EPwm4Regs.TBCTL.bit.PHSDIR = TB_UP;//TB_UP;
EPwm4Regs.TBCTL.bit.SYNCOSEL = 0; // syncin = syncout
EPwm4Regs.TBPHS.half.TBPHS = D23; //PHASE SHIFT=[(D2+D3)*TS/2]*TBPRD
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
}
else
{
D3=0;
}
//**********************************************************************************************************************************************************
// Read the contents Adc registers and store in the global variables
Voltage_V1 = AdcMirror.ADCRESULT0; // store global results
Voltage_nV2 = AdcMirror.ADCRESULT1;
// Reinitialize for next ADC sequence
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
}
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// INITIALIZE GPIOs
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
void Gpio_Select(void)
{
EALLOW;
GpioCtrlRegs.GPAMUX1.all = 0; // GPIO15 ... GPIO0 = General Puropse I/O
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // ePWM1A active
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // ePWM1B active
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // ePWM2A active
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // ePWM2B active
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // ePWM3A active
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // ePWM3B active
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // ePWM4A active
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // ePWM4B active
GpioCtrlRegs.GPAMUX2.all = 0; // GPIO31 ... GPIO16 = General Purpose I/O
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO28 = 1;
GpioCtrlRegs.GPBMUX1.all = 0; // GPIO38 ... GPIO32 = General Purpose I/O
GpioCtrlRegs.GPADIR.all = 0;
GpioCtrlRegs.GPBDIR.all = 0; // GPIO38 ... GPIO32 as inputs
GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1; // GPIO32 as output
EDIS;
}
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// INITIALIZE EPWM
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
void Setup_ePWM()
{
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
//*********************************************LEG1*****************************************************************
// TIME BASE CONTROL REGISTER
EPwm1Regs.TBCTL.all = 0; // default status
EPwm1Regs.TBCTL.bit.CLKDIV = 0x2; // CLKDIV = 4
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // HSPCLKDIV = 1
EPwm1Regs.TBCTL.bit.CTRMODE = 2; // up - down mode
EPwm1Regs.AQCTLA.all = 0x0060; // set ePWM1A on CMPA up
// clear ePWM1A on CMPA down
EPwm1Regs.TBPRD = (Period) ; // Period*2.. TBCLK COUNTS..=PERIOD..500Hz - PWM signal
// TBPRD = fcpu / (2*fPWM * CLKDIV * HSPCLKDIV)
// TPPRD = 150MHz / (2 * 500Hz *4) = 37500
EPwm1Regs.CMPA.half.CMPA = EPwm1Regs.TBPRD/2; // 50% duty cycle first
//
EPwm1Regs.DBRED = dead_band; // 10 microseconds delay
EPwm1Regs.DBFED = dead_band; // for rising and falling edge
EPwm1Regs.DBCTL.bit.OUT_MODE = 3; // ePWM1A = RED
EPwm1Regs.DBCTL.bit.POLSEL = 2; // S3=1 inverted signal at ePWM1B.. THIS GENERATES INVERTED SIGNAL.. NO NEED TO SET COMPARE B!
EPwm1Regs.DBCTL.bit.IN_MODE = 0; // ePWM1A = source for RED & FED
// Trip zone
EALLOW;
EPwm1Regs.TZSEL.bit.OSHT1 = 1; // Trip zone select
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
EDIS;
//*********************************************LEG2*****************************************************************
EPwm2Regs.TBCTL.all = 0; // default status
EPwm2Regs.TBCTL.bit.CLKDIV = 0x2; // CLKDIV = 4
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // HSPCLKDIV = 1
EPwm2Regs.TBCTL.bit.CTRMODE = 2; // up - down mode
EPwm2Regs.AQCTLA.all = 0x0060; // set ePWM2A on CMPA up
// clear ePWM2A on CMPA down
EPwm2Regs.TBPRD =(Period) ; // 500Hz - PWM signal
// TBPRD = fcpu / (2* 500Hz * CLKDIV * HSPCLKDIV)
// TPPRD = 150MHz / (2 * 500Hz * 1 * 1) = Period
EPwm2Regs.CMPA.half.CMPA= EPwm2Regs.TBPRD/2; // 50% duty cycle first
EPwm2Regs.DBRED = dead_band; // 10 microseconds delay
EPwm2Regs.DBFED = dead_band; // for rising and falling edge
EPwm2Regs.DBCTL.bit.OUT_MODE = 3; // ePWM1A = RED
EPwm2Regs.DBCTL.bit.POLSEL = 2; // S3=1 inverted signal at ePWM1B
EPwm2Regs.DBCTL.bit.IN_MODE = 0; // ePWM1A = source for RED & FED
//Trip zone
EALLOW;
EPwm2Regs.TZSEL.bit.OSHT1 = 1;
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
EDIS;
//*********************************************LEG3*****************************************************************
EPwm3Regs.TBCTL.all = 0; // default status
EPwm3Regs.TBCTL.bit.CLKDIV = 0x2; // CLKDIV = 4
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0; // HSPCLKDIV = 1
EPwm3Regs.TBCTL.bit.CTRMODE = 2; // up - down mode
EPwm3Regs.AQCTLA.all = 0x0060; // set ePWM1A on CMPA up
// clear ePWM1A on CMPA down
EPwm3Regs.TBPRD = (Period); // 2kHz - PWM signal
// TBPRD = fcpu / (2* 500Hz * CLKDIV * HSPCLKDIV)
// TPPRD = 150MHz / (2 * 500Hz * 1 * 1) = Period
EPwm3Regs.CMPA.half.CMPA = EPwm3Regs.TBPRD/2; // 50% duty cycle first
EPwm3Regs.DBRED = dead_band; // 10 microseconds delay
EPwm3Regs.DBFED = dead_band; // for rising and falling edge
EPwm3Regs.DBCTL.bit.OUT_MODE = 3; // ePWM1A = RED
EPwm3Regs.DBCTL.bit.POLSEL = 2; // S3=1 inverted signal at ePWM1B
EPwm3Regs.DBCTL.bit.IN_MODE = 0; // ePWM1A = source for RED & FED
// Trip zone
EALLOW;
EPwm3Regs.TZSEL.bit.OSHT1 = 1;
EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
EDIS;
//
//*********************************************LEG4*****************************************************************
EPwm4Regs.TBCTL.all = 0; // default status
EPwm4Regs.TBCTL.bit.CLKDIV = 0x2; // CLKDIV = 4
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0; // HSPCLKDIV = 1
EPwm4Regs.TBCTL.bit.CTRMODE = 2; // up - down mode
EPwm4Regs.AQCTLA.all = 0x0060; // set ePWM1A on CMPA up
// clear ePWM1A on CMPA down
EPwm4Regs.TBPRD = (Period) ; // 500Hz - PWM signal
// TBPRD = fcpu / (2*500HZ * CLKDIV * HSPCLKDIV)
// TPPRD = 150MHz / (2 * 500Hz * 1 * 1) = Period
EPwm4Regs.CMPA.half.CMPA = EPwm4Regs.TBPRD/2; // 50% duty cycle first
EPwm4Regs.DBRED = dead_band; // 10 microseconds delay
EPwm4Regs.DBFED = dead_band; // for rising and falling edge
EPwm4Regs.DBCTL.bit.OUT_MODE = 3; // ePWM1A = RED
EPwm4Regs.DBCTL.bit.POLSEL = 2; // S3=1 inverted signal at ePWM1B
EPwm4Regs.DBCTL.bit.IN_MODE = 0; // ePWM1A = source for RED & FED
//Trip zone
EALLOW;
EPwm4Regs.TZSEL.bit.OSHT1 = 1;
EPwm4Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm4Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
EDIS;
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
}
Thank you.
Harrye