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Phase shifted full bridge - PCMC TMS320f28069

Robert Rapp
Prodigy 30 points

Other Parts Discussed in Thread: TMS320F28069

I have designed a high-current buck converter using a TMS320F28069 but I am running into issues on very light loads (about 100 ma). I am using the PSFB-PCMC mode from the digital control library & it is designed to put out a few hundred Amps at 28 volts.

 

The converter runs at 100kHz (just like the HVPSFB kit) & the issues start happening with a <17% duty cycle. I believe this is the limitation imposed by the comparator that needs to wait the 346ns setup time.

 

After reading several posts here on the HVPSFB kit, I am wondering if anyone can point me to an example of a burst mode? Do you switch to just use the DAC and turn off the slope compensation ramp? Is it best to go to a custom voltage mode control (since I believe the switches are different in the default DP Library)?  Would the transition between the two control modes methods cause issues (jittering, instabilities, etc.) considering it should run at the rate of the ISR loop?

 

Any other recommendations on how to overcome this issue?

  • 0
    TI__Genius 10820 points

    Hi Robert,

    At very low loads the sensed current signal may be too noisy. You may want to try to get as clean a current feedback signal as possible. During run-time the comparator set-up time should not be an issue. Are you referring to the DAC settling time? Under steady state the DAC should have enough time from one cycle to the next to go back to its commanded value. You may also want to adjust the blanking window length, which limits the minimum possible duty cycle.

    If you have already tried above methods, you can try implementing burst mode in software. You can implement PWM duty mode and/or change to voltage mode control to implement burst mode when the load falls below a certain value and/or at start-up. As you rightly point, a seamless/glitchless transition between modes is very important. You will have to make sure you change the PWM configuration at the right time and close to a known 'good point' (CTR = 0/PRD) in the cycle.

    I hope this helps.

    Hrishi