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INL and DNL dual delfino question

Mauro Fantina
Genius 3800 points

Other Parts Discussed in Thread: TMS320F28377D

I read at page 47 of

SPRS880B –DECEMBER 2013–REVISED AUGUST 2014

at link http://www.ti.com/lit/gpn/tms320f28377d

and I don't understand how INL and DNL are equals to 12/16 bit modes

in the dual-delfino controller

Can someone help me

  • 0
    TI__Guru 60865 points

    Hi Mauro,

    The linearity for both modes is specified in LSBs.  The LSB size is 16x smaller for 16-bit mode vs 12-bit mode, so the linearity specification is effectively 16x better for 16-bit mode vs 12-bit mode.

  • 0 in reply to Devin Cottier
    Genius 3800 points

    I don't understand how increasing number of bits

    in the same hardware

    linearity get better.

  • 0 in reply to Mauro Fantina
    TI__Guru 60865 points

    Hi Mauro,

    The ADC operates differently in 12-bit mode and 16-bit mode.  For example, notice that the S+H capacitor values specified in the documentation are different for these two modes and that the number of cycles required to convert a 16-bit value is much higher than that required to convert a 12-bit value (not just 4 more cycles for 4 more bits). 16-bit mode also benefits from linearity trim, while 12-bit mode can't use the trim correctly (see the errata).